library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity cnt10 is
   port(clk:in std_logic;
        clr:in std_logic;
         ci:in std_logic;    						  --  carry in
         cq:out std_logic_vector(3 downto 0);  --  4wei ji 'shu jie guo
         co: out std_logic);    						  --  carry out
end cnt10;


architecture behav of cnt10 is
   signal cqi: std_logic_vector(3 downto 0):="0000";
begin
   process(clk,clr)
   begin
      if(clr='1') then
         cqi<="0000";
      elsif(clk'event and clk='1')then
         if(ci='1') then
            if(cqi="1001")then
               cqi<="0000";
            else 
               cqi<=cqi+1;
            end if;
         end if;
      end if;
   end process;
   cq<=cqi;
   co<='1' when cqi="1001" and ci='1' else '0';
end behav;