library ieee;
use ieee.std_logic_1164.all;

entity shifter is 
port(
  clk,load,left_right:  in std_logic;
  din: in std_logic_vector(3 downto 0);
  dout: out std_logic_vector(3 downto 0)
);
end ;


architecture synthesis of shifter is
signal shift_var:std_logic_vector(3 downto 0);
begin

process(load,left_right,din)
 begin
     if load='1' then
       shift_var<=din;
     elsif left_right='0' then
       shift_var(2 downto 0)<=din(3 downto 1);
       shift_var(3)<='0';
     else
       shift_var(3 downto 1)<=din(2 downto 0);
       shift_var(0)<='0';
      end if;

end process;

process(clk)
begin
if clk'event and clk='1' then
dout<=shift_var;
end if;
end process;

end synthesis;