{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 02 09:46:06 2005 " "Info: Processing started: Sat Jul 02 09:46:06 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off shifter -c shifter --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off shifter -c shifter --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 6 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register paths exist for clock clk" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "dout\[2\]~reg0 load clk 2.738 ns register " "Info: tsu for register dout\[2\]~reg0 (data pin = load, clock pin = clk) is 2.738 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.654 ns + Longest pin register " "Info: + Longest pin to register delay is 5.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns load 1 PIN PIN_Y21 4 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y21; Fanout = 4; PIN Node = 'load'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "" { load } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.697 ns) + CELL(0.870 ns) 5.654 ns dout\[2\]~reg0 2 REG LC_X1_Y1_N5 1 " "Info: 2: + IC(3.697 ns) + CELL(0.870 ns) = 5.654 ns; Loc. = LC_X1_Y1_N5; Fanout = 1; REG Node = 'dout\[2\]~reg0'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "4.567 ns" { load dout[2]~reg0 } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.957 ns 34.61 % " "Info: Total cell delay = 1.957 ns ( 34.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.697 ns 65.39 % " "Info: Total interconnect delay = 3.697 ns ( 65.39 % )" {  } {  } 0}  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "5.654 ns" { load dout[2]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.926 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 2.926 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.659 ns) + CELL(0.542 ns) 2.926 ns dout\[2\]~reg0 2 REG LC_X1_Y1_N5 1 " "Info: 2: + IC(1.659 ns) + CELL(0.542 ns) = 2.926 ns; Loc. = LC_X1_Y1_N5; Fanout = 1; REG Node = 'dout\[2\]~reg0'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "2.201 ns" { clk dout[2]~reg0 } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 43.30 % " "Info: Total cell delay = 1.267 ns ( 43.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.659 ns 56.70 % " "Info: Total interconnect delay = 1.659 ns ( 56.70 % )" {  } {  } 0}  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "2.926 ns" { clk dout[2]~reg0 } "NODE_NAME" } } }  } 0}  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "5.654 ns" { load dout[2]~reg0 } "NODE_NAME" } } } { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "2.926 ns" { clk dout[2]~reg0 } "NODE_NAME" } } }  } 0}