library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity time is
port(en,clk:in std_logic;
     h1,h0:out std_logic_vector(3 downto 0));
end;
architecture rtl of time is
begin process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
     if en='0' then cnt0:="0000";cnt1:="0000";
         elsif clk'event and clk='1' then
           if cnt0="0011" and cnt1="0010" then
              cnt0:="0000" ;cnt1:="0000";
            elsif cnt0<"1001" then cnt0:=cnt0+1;
            else  cnt0:="0000";cnt1:=cnt1+1;
         end if;
       end if;
    h1<=cnt1;h0<=cnt0;
  end process;
    
 end rtl;