library ieee;
use ieee.std_logic_1164.all;
entity TENNIS is
port(bain,bbin,clr,clk,souclk:in std_logic;
	ballout:out std_logic_vector(7 downto 0);
	countah,countal,countbh,countbl:out std_logic_vector(3 downto 0);
	lamp,speaker:out std_logic);
end;
architecture ful of TENNIS is

component sound  
port (clk,sig,en:in std_logic;
		sout:out std_logic);
end component;

component ballctrl 
port(clr,bain,bbin,serclka,serclkb,clk:in std_logic;
	bdout,serve,serclk,ballclr,ballen:out std_logic);
end component;

component ball
port(clk,clr,way,en:in std_logic;
		ballout:out std_logic_vector(7 downto 0));
end component;

component board  
port (ball,net,bclk,serve:in std_logic;
		couclk,serclk:out std_logic);
end component;

component cou10   
port(clk,clr:in std_logic;
	cout:out std_logic;
	qout:out std_logic_vector(3 downto 0));
end component;

component cou4  
port(clk,clr:in std_logic;
	cout:out std_logic;
	qout:out std_logic_vector(3 downto 0));
end component;

component mway  
port(servea,serveb:in std_logic;
	way:out std_logic);
end component;

signal net,couclkah,couclkal,couclkbh,couclkbl,cah,cbh:std_logic;
signal serve,serclka,serclkb,serclk,ballclr,bdout,way,ballen:std_logic;
signal bbll:std_logic_vector( 7 downto 0);
begin
net<=bbll(4);
uah:cou4  port map (couclkah,clr,cah,countah);
ual:cou10 port map (couclkal,clr,couclkah,countal);
ubh:cou4  port map (couclkbh,clr,cbh,countbh);
ubl:cou10 port map (couclkbl,clr,couclkbh,countbl);
ubda:board port map (bbll(0),net,bain,serve,couclkal,serclka);
ubdb:board port map (bbll(7),net,bbin,serve,couclkbl,serclkb);
ucpu:ballctrl port map (clr,bain,bbin,serclka,serclkb,clk,bdout,serve,serclk,ballclr,ballen);
uway:mway port map (serclka,serclkb,way);
uball: ball port map (clk,ballclr,way,ballen,bbll);
usound:sound port map(souclk,ballen,bdout,speaker);
ballout<=bbll;
lamp<=clk;
end;