# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		dccount_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "5.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:26:14  AUGUST 13, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION "5.0 SP1"
set_global_assignment -name VHDL_FILE "D:\\Quartus\\dccount\\dccount.vhd"

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Architect"
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name TOP_LEVEL_ENTITY dccount

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EPM7128SLC84-15"

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (VHDL)"

# ---------------------------------------------
# start EDA_TOOL_SETTINGS(eda_design_synthesis)

	# Analysis & Synthesis Assignments
	# ================================
	set_global_assignment -name EDA_INPUT_GND_NAME GROUND -section_id eda_design_synthesis
	set_global_assignment -name EDA_LMF_FILE mnt8_bas.lmf -section_id eda_design_synthesis

# end EDA_TOOL_SETTINGS(eda_design_synthesis)
# -------------------------------------------

# ---------------------------------------
# start EDA_TOOL_SETTINGS(eda_simulation)

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
	set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation

# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------

# --------------------------------------------
# start EDA_TOOL_SETTINGS(eda_timing_analysis)

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_timing_analysis
	set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_timing_analysis
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_timing_analysis

# end EDA_TOOL_SETTINGS(eda_timing_analysis)
# ------------------------------------------