Analysis & Synthesis report for dccount
Sat Aug 13 13:26:25 2005
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Failed - Sat Aug 13 13:26:25 2005             ;
; Quartus II Version          ; 5.0 Build 168 06/22/2005 SP 1 SJ Full Version ;
; Revision Name               ; dccount                                       ;
; Top-level Entity Name       ; dccount                                       ;
; Family                      ; MAX7000S                                      ;
+-----------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                          ;
+----------------------------------------------------------------------+-----------------+---------------+
; Option                                                               ; Setting         ; Default Value ;
+----------------------------------------------------------------------+-----------------+---------------+
; Device                                                               ; EPM7128SLC84-15 ;               ;
; Top-level entity name                                                ; dccount         ; dccount       ;
; Family name                                                          ; MAX7000S        ; Stratix       ;
; Type of Retiming Performed During Resynthesis                        ; Full            ;               ;
; Resynthesis Optimization Effort                                      ; Normal          ;               ;
; Physical Synthesis Level for Resynthesis                             ; Normal          ;               ;
; Use Generated Physical Constraints File                              ; On              ;               ;
; Use smart compilation                                                ; Off             ; Off           ;
; Create Debugging Nodes for IP Cores                                  ; off             ; off           ;
; Preserve fewer node names                                            ; On              ; On            ;
; Disable OpenCore Plus hardware evaluation                            ; Off             ; Off           ;
; Verilog Version                                                      ; Verilog_2001    ; Verilog_2001  ;
; VHDL Version                                                         ; VHDL93          ; VHDL93        ;
; State Machine Processing                                             ; Auto            ; Auto          ;
; Extract Verilog State Machines                                       ; On              ; On            ;
; Extract VHDL State Machines                                          ; On              ; On            ;
; Add Pass-Through Logic to Inferred RAMs                              ; On              ; On            ;
; NOT Gate Push-Back                                                   ; On              ; On            ;
; Power-Up Don't Care                                                  ; On              ; On            ;
; Remove Redundant Logic Cells                                         ; Off             ; Off           ;
; Remove Duplicate Registers                                           ; On              ; On            ;
; Ignore CARRY Buffers                                                 ; Off             ; Off           ;
; Ignore CASCADE Buffers                                               ; Off             ; Off           ;
; Ignore GLOBAL Buffers                                                ; Off             ; Off           ;
; Ignore ROW GLOBAL Buffers                                            ; Off             ; Off           ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A           ; Auto            ; Auto          ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A            ; Off             ; Off           ;
; Limit AHDL Integers to 32 Bits                                       ; Off             ; Off           ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A         ; Speed           ; Speed         ;
; Allow XOR Gate Usage                                                 ; On              ; On            ;
; Auto Logic Cell Insertion                                            ; On              ; On            ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4               ; 4             ;
; Auto Parallel Expanders                                              ; On              ; On            ;
; Auto Open-Drain Pins                                                 ; On              ; On            ;
; Remove Duplicate Logic                                               ; On              ; On            ;
; Auto Resource Sharing                                                ; Off             ; Off           ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A   ; 100             ; 100           ;
; Ignore translate_off and translate_on Synthesis Directives           ; Off             ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                   ; On              ; On            ;
+----------------------------------------------------------------------+-----------------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                ;
+----------------------------------+-----------------+-----------------+--------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path   ;
+----------------------------------+-----------------+-----------------+--------------------------------+
; dccount.vhd                      ; yes             ; User VHDL File  ; D:/Quartus/dccount/dccount.vhd ;
+----------------------------------+-----------------+-----------------+--------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Aug 13 13:26:21 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dccount -c dccount
Info: Found 2 design units, including 1 entities, in source file dccount.vhd
    Info: Found design unit 1: dccount-a
    Info: Found entity 1: dccount
Info: Elaborating entity "dccount" for the top level hierarchy
Info: (10035) Verilog HDL or VHDL information at dccount.vhd(30): object "ind_coil" declared but not used
Warning: VHDL Process Statement warning at dccount.vhd(60): signal "Hz" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Error: VHDL Process Statement error at dccount.vhd(45): Process Statement cannot contain both a sensitivity list and a Wait Statement
Warning: VHDL Process Statement warning at dccount.vhd(50): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 2 warnings
    Error: Processing ended: Sat Aug 13 13:26:25 2005
    Error: Elapsed time: 00:00:04