// arbit1.v

module arbit1 (clk, reset, chan0_ramaddr, chan0_dat_from_ram, chan0_dat_to_ram, chan1_ramaddr, chan1_dat_from_ram, chan1_dat_to_ram, address_preset, ram_rwn, ram_addr, ram_data_pins, data_rd, data_wr, up_data_to_ram, up_data_from_ram, sram_addr_strobe, rd_ack, wr_ack, ram_data_oe);

// System inputs.
input		clk;		// System clock.
input		reset;		// System reset.
	
// Control signals.
output 	[2:0]	rd_ack; 	// Acknowledge signal that read
					//  cycle is complete.
reg 		[2:0]	rd_ack;
output 	[2:0]	wr_ack; 	// Acknowledge pulse that write 
//  cycle is complete.
reg		[2:0]	wr_ack;

// RAM interface.
input 	[12:1]	chan0_ramaddr;// Channel 0 RAM address pointer.
wire 	[12:1]	chan0_ramaddr;
input 	[12:1]	chan1_ramaddr;// Channel 1 RAM address pointer.
wire 	[12:1]	chan1_ramaddr;
output 	[15:0]	chan0_dat_from_ram;// Channel 0 RAM read data.
reg		[15:0]	chan0_dat_from_ram;
output 	[15:0]	chan1_dat_from_ram;// Channel 0 RAM read data.
reg		[15:0]	chan1_dat_from_ram;
input 	[15:0]	chan0_dat_to_ram;	// Channel 0 RAM write data.
wire 	[15:0]	chan0_dat_to_ram;
output 	[15:0]	chan1_dat_to_ram;	// Channel 1 RAM write data.
wire 	[15:0]	chan1_dat_to_ram;
input 	[2:0] 	data_rd;	 	// RAM read request.
wire 	[2:0] 	data_rd;
input 	[2:0] 	data_wr;		// RAM write request.
wire 	[2:0] 	data_wr;
input	 	sram_addr_strobe;	// Signal to preload address
//  counter.
input 	[15:0] up_data_to_ram;	// Data to be written into
//  RAM.
output 	[15:0]	up_data_from_ram;	// Data read from RAM.
reg		[15:0]	up_data_from_ram;
input 	[12:0]	address_preset; 	// Microprocessor
//  address counter
//  preset input.
	
// RAM I/O ports.
output	ram_rwn;		// SRAM read/write control pin,
//  high = read.
output	[12:0]	ram_addr; 	// SRAM address pins.
reg		[12:0]	ram_addr;
inout	[7:0]	ram_data_pins;// RAM data to be written.
wire		[7:0]	ram_data_in;
reg		[7:0]	ram_data_out;
output		ram_data_oe;		// RAM output enable.
reg			ram_data_oe;

// Local variables.
reg		[3:0]	ram_state;
reg			ram_rdn;
reg		[11:0]	ram_addr_ctr;// Register to store auto-
//  incremented addresses. Counts
  					//  words.

parameter ram_state_idle	=	0;
parameter ram_state1		=	1;
parameter ram_state2		=	2;
parameter ram_state3		=	3;
parameter ram_state4		=	4;
parameter ram_state5		=	5;
parameter ram_state6		=	6;
parameter ram_state7		=	7;
parameter ram_state8		=	8;
parameter ram_state9		=	9;
parameter ram_state10		=	10;
parameter ram_state11		=	11;
parameter ram_state12		=	12;
parameter ram_state13		=	13;
parameter ram_state14		=	14;
parameter ram_state15		=	15;

assign ram_rwn = ~ram_rdn;	// Active high local signal.

// Control of SRAM data pins.
assign ram_data_pins 	= ram_data_oe ? ram_data_out : 8'bz;
assign ram_data_in	= ram_data_pins;

	always @ (posedge clk or posedge reset)
	begin
		if (reset)
		begin
			ram_state 	<= 	ram_state_idle;
			ram_rdn	<=	0;
			ram_addr	<=	0;
			ram_data_out <=	0;
			rd_ack	 	<=	0;
			wr_ack	 	<=	0;
			ram_data_oe	<=	0;
		end
		else begin
		
		case (ram_state)
		ram_state_idle:
		begin
			begin
			ram_rdn	<=	0;
			ram_addr	<=	0;
			ram_data_out	<=	0;
			ram_data_oe	<=	0;
			end

			if (data_rd[0])
			begin
			ram_rdn	<=	0;
			ram_addr	<=	{chan0_ramaddr, 1'b0};
			ram_state	<=	ram_state1;
			end
			
			else if (data_rd[1])
			begin
			ram_rdn	<=	0;
			ram_addr	<=	{chan1_ramaddr, 1'b0};
			ram_state	<=	ram_state3;
			end

			else if (data_wr[0])
			begin
			ram_rdn	<=	1;
			ram_addr	<=	{chan0_ramaddr, 1'b0};
			ram_data_out <=	chan0_dat_to_ram[7:0];
			ram_data_oe	<=	1;
			ram_state	<=	ram_state5;
			end

			else if (data_wr[1])
			begin
			ram_rdn	<=	1;
			ram_addr	<=	{chan1_ramaddr, 1'b0};
			ram_data_out <=	chan1_dat_to_ram[7:0];
			ram_data_oe	<=	1;
			ram_state	<=	ram_state8;
			end

			else if (data_rd[2])// Microprocessor
//  read request.
			begin
			ram_rdn	<=	0;
			ram_addr	<=	{ram_addr_ctr, 1'b0};
			ram_state	<=	ram_state11;
			end

			else if (data_wr[2])// Microprocessor
//  write request.
			begin
			ram_rdn	<=	1;
			ram_addr	<=	{ram_addr_ctr, 1'b0};
			ram_data_out <=	up_data_from_ram[7:0];
			ram_data_oe	<=	1;
			ram_state	<=	ram_state13;
			end

			else			// Default.
			ram_state	 <=	ram_state_idle;

		end
			
// Read channel 0.
		ram_state1:
			begin
			ram_rdn	<=	0;
			ram_addr	<=	{chan0_ramaddr, 1'b1};
			chan0_dat_from_ram[7:0] <=	ram_data_in;
			rd_ack[0]	<=	1;	// Issue early.
			ram_state	<=	ram_state2;
			end
			
		ram_state2:
			begin
			ram_rdn	<=	0;
			ram_addr	<=	{chan0_ramaddr, 1'b1};
			chan0_dat_from_ram[15:8] <= ram_data_in;
			rd_ack[0]	<=	1; 	// Hold ack until
 							//  read is released.
			if (data_rd[0])
			ram_state	<=	ram_state2; 	// Hold until 
// rd
// released.
			else
			begin
			rd_ack[0]	<=	0;	// Release ack.
			ram_state	<=	ram_state_idle;
			end
			end

// Read channel 1.
		ram_state3:
			begin
			ram_rdn	<=	0;
			ram_addr	<=	{chan1_ramaddr, 1'b1};
			chan1_dat_from_ram[7:0] <=	ram_data_in;
			rd_ack[1]	<=	1;	// Issue early.
			ram_state	<=	ram_state4;
			end
			
		ram_state4:
			begin
			ram_rdn	<=	0;
			ram_addr	<=	{chan1_ramaddr, 1'b1};
			chan1_dat_from_ram[15:8] <= ram_data_in;
			rd_ack[1]	<=	1; 	// Hold ack until
 							//  read is released.
			if (data_rd[1]) // Hold until rd released.
			ram_state	<=	ram_state4;	
			else
			begin
			rd_ack[1]	<=	0;	// Release ack.
			ram_state	<=	ram_state_idle;
			end
			end

// Write channel 0.
		ram_state5:
			begin
			ram_rdn	<=	0;
			ram_addr	<=	{chan0_ramaddr, 1'b0};
			ram_data_out <=	chan1_dat_to_ram[7:0];
			ram_data_oe	<=	1;
			ram_state	<=	ram_state6;
			end

		ram_state6:
			begin
			ram_rdn	<=	1;
			ram_addr	<=	{chan0_ramaddr, 1'b1};
			ram_data_out <=	chan1_dat_to_ram[15:8];
			ram_data_oe	<=	1;
			wr_ack[0]	<=	1;	// Release early.
			ram_state	<=	ram_state7;
			end

		ram_state7:
			begin
			ram_rdn	<=	0;
			ram_addr	<=	{chan1_ramaddr, 1'b1};
			ram_data_out <=	chan1_dat_to_ram[15:8];
			ram_data_oe	<=	1;
			wr_ack[0]	<=	1; 	// Hold ack until
//  write is
//  released.
			if (data_wr[0]) // Hold until wr released. 
			ram_state	<=	ram_state7;
			else
			begin
			wr_ack[0]	<=	0;	// Release ack.
			ram_state	<=	ram_state_idle;
			end
			end

// Write channel 1.
		ram_state8:
			begin
			ram_rdn	<=	0;
			ram_addr	<=	{chan1_ramaddr, 1'b0};
			ram_data_out <=	chan1_dat_to_ram[7:0];
			ram_data_oe	<=	1;
			ram_state	<=	ram_state9;
			end

		ram_state9:
			begin
			ram_rdn	<=	1;
			ram_addr	<=	{chan1_ramaddr, 1'b1};
			ram_data_out <=	chan1_dat_to_ram[15:8];
			ram_data_oe	<=	1;
			wr_ack[1]	<=	1;	// Release early.
			ram_state	<=	ram_state10;
			end

		ram_state10:
			begin
			ram_rdn	<=	0;
			ram_addr	<=	{chan1_ramaddr, 1'b1};
			ram_data_out <=	chan1_dat_to_ram[15:8];
			ram_data_oe	<=	1;
			wr_ack[1]	<=	1; // Hold ack until
 						   //  write is released.
			if (data_wr[1]) // Hold until wr released.
			ram_state	 <=	ram_state10;
			else
			begin
			wr_ack[1]	 <=	0;	// Release ack.
			ram_state	 <=	ram_state_idle;
			end
			end

// Microprocessor initiated read.
		ram_state11:
			begin
			ram_rdn	<=	0;
			ram_addr	<=	{ram_addr_ctr, 1'b1};
			up_data_from_ram[7:0]	<=	ram_data_in;
			ram_state	<=	ram_state12;
			end
			
		ram_state12:	// Address counter incremented
//  in this state.
			begin
			ram_rdn	 <=	0;
			ram_addr	 <=	{ram_addr_ctr, 1'b1};
			rd_ack[2]			<=	1;
			up_data_from_ram[15:8]	<=	ram_data_in;
			ram_state	 <=	ram_state_idle;
			end

// Microprocessor initiated write.
		ram_state13:
			begin
			ram_rdn	<=	0;
			ram_addr	<=	{ram_addr_ctr, 1'b0};
			ram_data_out <=	up_data_to_ram[7:0];
			ram_data_oe	<=	1;
			ram_state	<=	ram_state14;
			end

		ram_state14:
			begin
			ram_rdn	<=	1;
			ram_addr	<=	{ram_addr_ctr, 1'b1};
			ram_data_out <=	up_data_to_ram[15:8];
			ram_data_oe	<=	1;
			wr_ack[2]	<=	1; // Release early.
			ram_state	<=	ram_state15;
			end

		ram_state15:	// Address counter incremented
//  in this state.
		begin
		ram_rdn	    	<=	0;
		ram_addr		<=	{ram_addr_ctr, 1'b1};
		ram_data_out		<=	up_data_to_ram[15:8];
		ram_data_oe		<=	1;
		wr_ack[2]		<=	0;
		ram_state		<=	ram_state_idle;
		end

		default: 
ram_state		<=	ram_state_idle;
					
		endcase
		end
		end

// Increment address counter when microprocessor reads or
//   writes.
	always @ (posedge clk or posedge reset)
	begin
		if (reset)
			ram_addr_ctr	<=	0;
		else if	(sram_addr_strobe)
			ram_addr_ctr	<=	address_preset;
		else if 	((ram_state == ram_state12) | 
   				 (ram_state == ram_state15))
			ram_addr_ctr	<=	ram_addr_ctr + 1;
	end

endmodule