%{/* * Copyright (c) 1999-2002 moe * *    This source code is free software; you can redistribute it *    and/or modify it in source code form under the terms of the GNU *    General Public License as published by the Free Software *    Foundation; either version 2 of the License, or (at your option) *    any later version. * *    This program is distributed in the hope that it will be useful, *    but WITHOUT ANY WARRANTY; without even the implied warranty of *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the *    GNU General Public License for more details. * *    You should have received a copy of the GNU General Public License *    along with this program; if not, write to the Free Software *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */#include <string>#include <list>#include <vector>#include "verilog.h"  using namespace std;void       verilog_error(char *str);extern int verilog_lex();extern unsigned int line;extern string       file;extern void lex_start_table();extern void lex_end_table();#include "Verilog.hh" moe::Verilog::Module*   module_;moe::Verilog::Function* function_;moe::Verilog::Instance* instance_;static void error(char* text)  {//    yyerror(text);  }%}%union {  map<string,moe::Verilog::Net*>*    nets;  moe::Verilog::Case::Item*          item;  vector<moe::Verilog::Case::Item*>* items;  moe::Verilog::Event*               evexpr;    vector<moe::Verilog::Event*>*      evexprs;  moe::Verilog::EventStatement*      evstat;  moe::Verilog::Expression*          expr;  vector<moe::Verilog::Expression*>* exprs;  moe::Verilog::Instance*            inst;  vector<moe::Verilog::Instance*>*   insts;  moe::Verilog::Net::nrm_*           regvar;  list<moe::Verilog::Net::nrm_*>*    regvars;  moe::Verilog::Statement*           stat;  vector<moe::Verilog::Statement*>*  stats;  list<char*>*                       texts;  char*                              text;  int                                type;};%token <text> DIDENTIFIER HIDENTIFIER IDENTIFIER PORTNAME SYSTEM_IDENTIFIER STRING%token <text> NUMBER%token <text> REALTIME%token K_ATCOMM%token K_LS%token K_RS%token K_ALS%token K_ARS%token K_POW%token K_LE%token K_GE%token K_EG%token K_SG%token K_EQ%token K_NE%token K_CEQ%token K_CNE%token K_LOR%token K_LAND%token K_NOR%token K_NXOR%token K_NXOR%token K_NAND%token K_TRIGGER%token K_AAA%token K_SIGNED%token K_UNSIGNED%token K_ATTRIBUTE%token K_PLUSRANGE%token K_MINUSRANGE%token K_always%token K_and%token K_assign%token K_automatic%token K_begin%token K_buf%token K_bufif0%token K_bufif1%token K_case%token K_casex%token K_casez%token K_cmos%token K_default%token K_deassign%token K_defparam%token K_disable%token K_edge%token K_else%token K_end%token K_endcase%token K_endconfig%token K_endfunction%token K_endgenerate%token K_endmodule%token K_endprimitive%token K_endspecify%token K_endtable%token K_endtask%token K_event%token K_for%token K_force%token K_forever%token K_fork%token K_function%token K_generate%token K_genvar%token K_highz0%token K_highz1%token K_if%token K_ifnone%token K_initial%token K_inout%token K_input%token K_integer%token K_join%token K_large%token K_library%token K_localparam%token K_macromodule%token K_medium%token K_module%token K_nand%token K_negedge%token K_nmos%token K_nor%token K_not%token K_notif0%token K_notif1%token K_or%token K_output%token K_parameter%token K_pmos%token K_posedge%token K_primitive%token K_pull0%token K_pull1%token K_pulldown%token K_pullup%token K_rcmos%token K_real%token K_realtime%token K_reg%token K_release%token K_repeat%token K_rnmos%token K_rpmos%token K_rtran%token K_rtranif0%token K_rtranif1%token K_scalared%token K_signed%token K_small%token K_specify%token K_specparam%token K_strong0%token K_strong1%token K_supply0%token K_supply1%token K_table%token K_task%token K_time%token K_tran%token K_tranif0%token K_tranif1%token K_tri%token K_tri0%token K_tri1%token K_triand%token K_trior%token K_trireg%token K_unsigned%token K_vectored%token K_wait%token K_wand%token K_weak0%token K_weak1%token K_while%token K_wire%token K_wor%token K_xnor%token K_xor%token K_design%token K_instance%token K_cell%token K_use%token K_liblist%token K_include%token K_incdir%token K_countdrivers%token K_getpattern%token K_incsave%token K_input%token K_key%token K_list%token K_log%token K_nokey%token K_nolog%token K_reset%token K_reset_count%token K_reset_value%token K_restart%token K_save%token K_scale%token K_scope%token K_showscopes%token K_showvars%token K_sreadmemb%token K_sreadmemh%token K_D_attribute%type <text> attribute_instance_opt%type <text> identifier//%type <text> port_opt%type <texts> list_of_variables%type <text> net_decl_assign%type <texts> net_decl_assigns%type <regvar>  register_variable%type <regvars> register_variable_list%type <item>  case_item%type <items> case_items%type <inst>  module_instance%type <insts> module_instance_list%type <expr>  expression expr_primary%type <expr>  lavalue lpvalue%type <exprs> expression_list%type <exprs> range range_opt%type <type>  net_type%type <type>  v2k_net_type%type <type> gatetype%type <type> port_type%type <exprs> range_or_type_opt%type <evexprs> event_expression_list%type <evexpr> event_expression%type <evstat> event_control%type <stat>  statement statement_opt%type <stats> statement_list%type <nets>  block_item_decls_opt%type <nets>  block_item_decls%type <nets>  block_item_decl////////////////////////////////////////////////////////////////////////%right '?' ':'%left K_LOR%left K_LAND%left '|'%left '^' K_NXOR K_NOR%left '&' K_NAND%left K_EQ K_NE K_CEQ K_CNE%left K_GE K_LE '<' '>'%left K_LS K_RS%left K_ALS K_ARS%left '+' '-'%left '*' '/' '%'%left K_POW%left UNARY_PREC////////////////////////////////////////////////////////////////////////%nonassoc less_than_K_else%nonassoc K_else////////////////////////////////////////////////////////////////////////%%////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////main: source_file|;source_file: description| source_file description;description: module| udp_primitive{  error("not supported.");}| K_D_attribute '(' IDENTIFIER ',' STRING ',' STRING ')'{  error("not supported.");  delete $3;  delete $5;  delete $7;};module: K_module IDENTIFIER{  module_ =source_->addModule( $2 );  delete $2;}list_of_ports_opt ';' module_item_list_opt K_endmodule;module_item_list_opt: module_item_list|;module_item_list: module_item_list module_item| module_item;port_item: port_type range_opt list_of_variables{  moe::Verilog::Expression* msb;  moe::Verilog::Expression* lsb;  list<char*>::iterator i;  for( i=$3->begin();i!=$3->end();++i )    {      if( $2!=NULL )	{	  msb =(*$2)[0]->clone();	  lsb =(*$2)[1]->clone();	}      else	{	  msb =NULL;	  lsb =NULL;	}      module_->newNet(*i,moe::Verilog::Net::IMPLICIT,msb,lsb,$1);      delete *i;    }    if( $2!=NULL )    {      delete (*$2)[0];      delete (*$2)[1];      delete $2;    }  delete $3;}| port_type v2k_net_type range_opt list_of_variables{ // Verilog-2000 enhancements  moe::Verilog::Expression* msb;  moe::Verilog::Expression* lsb;  list<char*>::iterator i;  for( i=$4->begin();i!=$4->end();++i )    {      if( $3!=NULL )	{	  msb =(*$3)[0]->clone();	  lsb =(*$3)[1]->clone();	}      else	{	  msb =NULL;	  lsb =NULL;	}      module_->newNet(*i,$2,msb,lsb,$1);      delete *i;    }  if( $3!=NULL )    {      delete (*$3)[0];      delete (*$3)[1];      delete $3;    }  delete $4;}| port_type K_signed range_opt list_of_variables{ // Verilog-2000 enhancements  moe::Verilog::Expression* msb;  moe::Verilog::Expression* lsb;  list<char*>::iterator i;  for( i=$4->begin();i!=$4->end();++i )    {      if( $3!=NULL )	{	  msb =(*$3)[0]->clone();	  lsb =(*$3)[1]->clone();	}      else	{	  msb =NULL;	  lsb =NULL;	}      module_->newNet(*i,moe::Verilog::Net::IMPLICIT,msb,lsb,$1,		      NULL,NULL,true);      delete *i;    }  if( $3!=NULL )    {      delete (*$3)[0];      delete (*$3)[1];      delete $3;    }  delete $4;}| port_type K_signed v2k_net_type range_opt list_of_variables{ // Verilog-2000 enhancements  moe::Verilog::Expression* msb;  moe::Verilog::Expression* lsb;  list<char*>::iterator i;  for( i=$5->begin();i!=$5->end();++i )    {      if( $4!=NULL )	{	  msb =(*$4)[0]->clone();	  lsb =(*$4)[1]->clone();	}      else	{	  msb =NULL;	  lsb =NULL;	}      module_->newNet(*i,$3,msb,lsb,$1,NULL,NULL,true);      delete *i;    }  if( $4!=NULL )    {      delete (*$4)[0];      delete (*$4)[1];      delete $4;    }  delete $5;};module_item: port_item ';'| net_type range_opt list_of_variables ';'{  moe::Verilog::Expression* msb;  moe::Verilog::Expression* lsb;  list<char*>::iterator i;  for( i=$3->begin();i!=$3->end();++i )    {      if( $2!=NULL )	{	  msb =(*$2)[0]->clone();	  lsb =(*$2)[1]->clone();	}      else	{	  msb =NULL;	  lsb =NULL;	}      module_->newNet(*i,$1,msb,lsb,moe::Verilog::Net::PRIVATE);      delete *i;    }  if( $2!=NULL )    {      delete (*$2)[0];      delete (*$2)[1];      delete $2;    }  delete $3;}| net_type range_opt net_decl_assigns ';'{  moe::Verilog::Expression* msb;  moe::Verilog::Expression* lsb;  list<char*>::iterator i;  for( i=$3->begin();i!=$3->end();++i )    {      if( $2!=NULL )	{	  msb =(*$2)[0]->clone();	  lsb =(*$2)[1]->clone();	}      else	{	  msb =NULL;	  lsb =NULL;	}      module_->newNet(*i,$1,msb,lsb,moe::Verilog::Net::PRIVATE);      delete *i;    }  if( $2!=NULL )    {      delete (*$2)[0];      delete (*$2)[1];      delete $2;    }  delete $3;}| K_reg range_opt register_variable_list ';'{  moe::Verilog::Expression* msb;  moe::Verilog::Expression* lsb;  list<moe::Verilog::Net::nrm_*>::iterator i;  for( i=$3->begin();i!=$3->end();++i )    {      if( $2!=NULL )	{	  msb =(*$2)[0]->clone();	  lsb =(*$2)[1]->clone();	}      else	{	  msb =NULL;	  lsb =NULL;	}            module_->newNet((*i)->name,(*i)->type,msb,lsb,moe::Verilog::Net::PRIVATE,		      (((*i)->start!=NULL)?(*i)->start->clone():NULL),		      (((*i)->end!=NULL)?(*i)->end->clone():NULL));      delete *i;    }    if( $2!=NULL )    {      delete (*$2)[0];      delete (*$2)[1];      delete $2;    }  delete $3;}| net_type K_signed range_opt list_of_variables ';'{ // Verilog-2000 enhancements  moe::Verilog::Expression* msb;  moe::Verilog::Expression* lsb;  list<char*>::iterator i;  for( i=$4->begin();i!=$4->end();++i )    {      if( $3!=NULL )	{	  msb =(*$3)[0]->clone();	  lsb =(*$3)[1]->clone();	}      else	{	  msb =NULL;	  lsb =NULL;	}      module_->newNet(*i,$1,msb,lsb,moe::Verilog::Net::PRIVATE,		      NULL,NULL,true);      delete *i;    }  if( $3!=NULL )    {      delete (*$3)[0];      delete (*$3)[1];      delete $3;    }  delete $4;}| net_type K_signed range_opt net_decl_assigns ';'{ // Verilog-2000 enhancements  moe::Verilog::Expression* msb;  moe::Verilog::Expression* lsb;  list<char*>::iterator i;  for( i=$4->begin();i!=$4->end();++i )    {      if( $3!=NULL )	{	  msb =(*$3)[0]->clone();	  lsb =(*$3)[1]->clone();	}      else	{	  msb =NULL;	  lsb =NULL;	}      module_->newNet(*i,$1,msb,lsb,moe::Verilog::Net::PRIVATE,		      NULL,NULL,true);      delete *i;    }  if( $3!=NULL )    {      delete (*$3)[0];      delete (*$3)[1];      delete $3;    }  delete $4;}| K_reg K_signed range_opt register_variable_list ';'{ // Verilog-2000 enhancements  moe::Verilog::Expression* msb;  moe::Verilog::Expression* lsb;  list<moe::Verilog::Net::nrm_*>::iterator i;  for( i=$4->begin();i!=$4->end();++i )    {      if( $3!=NULL )	{	  msb =(*$3)[0]->clone();	  lsb =(*$3)[1]->clone();	}      else	{	  msb =NULL;	  lsb =NULL;	}            module_->newNet((*i)->name,(*i)->type,msb,lsb,moe::Verilog::Net::PRIVATE,		      (((*i)->start!=NULL)?(*i)->start->clone():NULL),		      (((*i)->end!=NULL)?(*i)->end->clone():NULL),		      true);      delete *i;    }    if( $3!=NULL )    {      delete (*$3)[0];      delete (*$3)[1];      delete $3;    }  delete $4;}| K_integer list_of_variables ';'{  list<char*>::iterator i;  for( i=$2->begin();i!=$2->end();++i )    {      module_->newNet(*i,moe::Verilog::Net::INTEGER,		      NULL,NULL,moe::Verilog::Net::PRIVATE);      delete *i;    }  delete $2;}| K_parameter parameter_assign_list ';'| K_assign drive_strength_opt delay3_opt assign_list ';'| IDENTIFIER parameter_value_opt attribute_instance_opt module_instance_list ';'{  vector<moe::Verilog::Instance*>::iterator i;