library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
  component div1024--1Hz_generator component
  Port( clk: in std_logic;--from system clock(1024Hz)
        f1hz : out std_logic);-- 1Hz output signal
  end component;
  component count60--i/o declaraction of component "count60" 
  Port(carry: in std_logic;--from 1Hz input clock or the full_index of second/minute
         Rst: in std_logic;--initialization
       times: out integer range 0 to 59;
        full: out std_logic);-- carry_out signal
  end component;  
  component count24--i/o declaraction of component "count24" 
  Port(carry: in std_logic;--from 1Hz input clock or the full_index of second/minute
         Rst: in std_logic;--initialization
       times: out integer range 0 to 23;
        full: out std_logic);-- carry_out signal
  end component;
  component alarm_set--i/o declaraction of component "set"   
  Port(rst,hz1: in std_logic;--clock 
       alarm,ok: in std_logic;--keep pushing to declare alarm set
       sec_tune: in std_logic;-- keep pushing to declare second tuning
       min_tune: in std_logic;-- keep pushing to declare minute tuning 
       hour_tune: in std_logic; --keep pushing to declare hour tuning
       sec,min: out integer range 0 to 59;
       hour: out integer range 0 to 23);
  end component;   
  component stop_watch--i/o declaraction of component "stop"   
  Port(rst,hz1: in std_logic;--system clock 1Hz
      stop: in std_logic;--keep pushing to declare stop setting
      ok: in std_logic;--keep pushing to declare stop setting
      sec_tune: in std_logic;--pushing button to tune seconds
      min_tune: in std_logic;--pushing button to tune minutes
      hour_tune: in std_logic;--pushing button to tune hours
      stop_sec,stop_min: out integer range 0 to 59;
      stop_hour: out integer range 0 to 23;      
      index: out std_logic; 
      disp: out std_logic);                 
  end component;
  component i60bcd--i/o declaraction of component "i60bcd" 
  port (interg : in integer range 0 to 59;--interger number
           ten : out std_logic_vector (3 downto 0) ;--decimal bit
           one : out std_logic_vector (3 downto 0) );--individual bit
  end component;  
  component i24bcd--i/o declaraction of component "i24bcd" 
  port (interg : in integer range 0 to 23;--interger number
           ten : out std_logic_vector (3 downto 0) ;--decimal bit
           one : out std_logic_vector (3 downto 0) );--individual bit
  end component; 
  component scan4--i/o declaraction of component "scan4"   
  port (rst,clk : in STD_LOGIC;
        a,b,c,d: in STD_LOGIC_vector(6 downto 0);
        pa,pb,pc,pd : out STD_LOGIC;
        mux_out: out STD_LOGIC_vector(6 downto 0));
  end component;  
  component scan2--i/o declaraction of component "scan2"   
  port (rst,clk : in STD_LOGIC;
        a,b: in STD_LOGIC_vector(6 downto 0);
        pa,pb: out STD_LOGIC;
        mux_out: out STD_LOGIC_vector(6 downto 0));
  end component;  
  component bin2led--i/o declaraction of component "bin2led"   
  port (bin : in std_logic_vector (3 downto 0);--internal binary number
        led : out std_logic_vector (6 downto 0) );--7_segments led display
  end component;  
end my_pkg;