?? d_in.vhd
字號:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
entity D_IN is
port (
DATA : out std_logic; -- Input Register
DIN : in std_logic; -- Digital input
CLK : in std_logic -- Sampling Clock
);
end D_IN;
architecture rtl of D_IN is
begin
process(CLK)
begin
if (CLK'event and CLK = '1') then
DATA <= DIN ;
end if ;
end process;
end rtl;?? 快捷鍵說明
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