/* -------------------------------------------------------------
	7Segment-LED Controller			Verilog-HDL Version
	FileName = DispCont.v

	M.YOSHIDA				15.MAY.2005		REV	1.0
------------------------------------------------------------- */
//	define Declaration
`define		SEG_VALUE0		8'b1100_0000
`define		SEG_VALUE1		8'b1111_1001
`define		SEG_VALUE2		8'b1010_0100
`define		SEG_VALUE3		8'b1011_0000
`define		SEG_VALUE4		8'b1001_1001
`define		SEG_VALUE5		8'b1001_0010
`define		SEG_VALUE6		8'b1000_0010
`define		SEG_VALUE7		8'b1111_1000
`define		SEG_VALUE8		8'b1000_0000
`define		SEG_VALUE9		8'b1001_1000
`define		SEG_VALUEA		8'b1000_1000
`define		SEG_VALUEB		8'b1000_0011
`define		SEG_VALUEC		8'b1100_0110
`define		SEG_VALUED		8'b1010_0001
`define		SEG_VALUEE		8'b1000_0110
`define		SEG_VALUEF		8'b1000_1110
`define		SEG_VALUEN		8'b1111_1111
`define		SEG_VALUEDP		8'b0111_1110

//	Module Declaration
module	DispCont	(	clk, rstn, data_in, dis, matrix_db, matrix_sel );

    //	port declaration
	input				clk, rstn, dis;
	input	[15:0]		data_in;
	output	[7:0]		matrix_db;
	output	[3:0]		matrix_sel;

    //	reg & wire declaration
	reg		[17:0]		sel_counter;
	reg		[7:0]		matrix_db;
	reg		[7:0]		seg_buff;
	reg		[3:0]		sel_value;
	
	/*	------------	matrix_sel declaration		------------	*/
	assign	matrix_sel[0]	=	!( sel_counter[17:16] == 2'b00 );
	assign	matrix_sel[1]	=	!( sel_counter[17:16] == 2'b01 );
	assign	matrix_sel[2]	=	!( sel_counter[17:16] == 2'b10 );
	assign	matrix_sel[3]	=	!( sel_counter[17:16] == 2'b11 );

	always	@( posedge clk or negedge rstn )	begin
		if( !rstn )	begin
		//	reset state
			sel_counter	<=	18'b0;
		end
		else	begin
		//	normal state
			sel_counter	<=	sel_counter + 1'b1;
		end
	end
	
	/*	------------	matrix_db declaration		------------	*/
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn )	begin
		//	reset state
			matrix_db	<=	~( `SEG_VALUE0 );
		end
		else if( dis )	begin
		//	enable segment
			matrix_db	<=	~( `SEG_VALUEN );
		end
		else	begin
		//	disable segment
			matrix_db	<=	~( seg_buff );
		end
	end
	
	/*	------------	seg_buff declaration		------------	*/
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn )	begin
		//	reset state
			seg_buff	<=	`SEG_VALUEDP;
		end
		else	begin
		//	normal state
			case	( sel_value )
			
				4'b0000:	begin	seg_buff	<=	`SEG_VALUE0;	end
				4'b0001:	begin	seg_buff	<=	`SEG_VALUE1;	end
				4'b0010:	begin	seg_buff	<=	`SEG_VALUE2;	end
				4'b0011:	begin	seg_buff	<=	`SEG_VALUE3;	end
				4'b0100:	begin	seg_buff	<=	`SEG_VALUE4;	end
				4'b0101:	begin	seg_buff	<=	`SEG_VALUE5;	end
				4'b0110:	begin	seg_buff	<=	`SEG_VALUE6;	end
				4'b0111:	begin	seg_buff	<=	`SEG_VALUE7;	end
				4'b1000:	begin	seg_buff	<=	`SEG_VALUE8;	end
				4'b1001:	begin	seg_buff	<=	`SEG_VALUE9;	end
				4'b1010:	begin	seg_buff	<=	`SEG_VALUEA;	end
				4'b1011:	begin	seg_buff	<=	`SEG_VALUEB;	end
				4'b1100:	begin	seg_buff	<=	`SEG_VALUEC;	end
				4'b1101:	begin	seg_buff	<=	`SEG_VALUED;	end
				4'b1110:	begin	seg_buff	<=	`SEG_VALUEE;	end
				4'b1111:	begin	seg_buff	<=	`SEG_VALUEF;	end

				default:	begin	seg_buff	<=	`SEG_VALUEN;	end
				
			endcase
		end
	end

	/*	------------	sel_value declaration		------------	*/
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn )	begin
		//	reset	state
			sel_value	<=	4'b0;
		end
		else	begin
		//	normal	state
			case( sel_counter[17:16] )
			
				2'b00:		begin	sel_value	<=	data_in[3:0];	end		//	SEGMENT1
				2'b01:		begin	sel_value	<=	data_in[7:4];	end		//	SEGMENT10
				2'b10:		begin	sel_value	<=	data_in[11:8];	end		//	SEGMENT100
				2'b11:		begin	sel_value	<=	data_in[15:12];	end		//	SEGMENT1000

				default:	begin	sel_value	<=	4'b0;	end
								
			endcase		
		end
	end	
	
endmodule