/* -----------------------------------------------------------------
	SX-USB2 System Controller		TAB = 4;
	Verilog-HDL Version

	Synthesis & Fitter tool = "QuartusII5.0WE"

	FileName = LFSR_top.v
	
	M.YOSHIDA				10.MAY.2005		REV	0.0
----------------------------------------------------------------- */
//	Define Declaration
//	Module Declaration
module	LFSR_top(		clk48m_c,
						rstn,
						rst1n,
						
						clk14p,
						pll5_out0,
						pll5_out1,
						pll5_fbin,
						ssram1_ab,
						ssram1_db,
						ssram1_bwan,
						ssram1_bwbn,
						ssram1_bwcn,
						ssram1_bwdn,
						ssram1_wen,
						ssram1_cken,
						ssram1_adv,
						ssram1_oen,
						ssram1_csn,

						clk6p,
						pll6_out0,
						pll6_out1,
						pll6_fbin,
						ssram2_ab,
						ssram2_db,
						ssram2_bwan,
						ssram2_bwbn,
						ssram2_bwcn,
						ssram2_bwdn,
						ssram2_wen,
						ssram2_cken,
						ssram2_adv,
						ssram2_oen,
						ssram2_csn,
						
						dummy,
						
						seg_db,
						seg_sel,
						led

				);

	//	Parameter  Declaration
	//	Port declaration
	//	System Port
	input							clk48m_c;
	input							rstn, rst1n;

	//	External SSRAM1 Port
	input							clk14p;
	output							pll5_out0;
	output							pll5_out1;
	input							pll5_fbin;
	output	[19:0]					ssram1_ab;
	inout	[35:0]					ssram1_db;
	output							ssram1_bwan;
	output							ssram1_bwbn;
	output							ssram1_bwcn;
	output							ssram1_bwdn;
	output							ssram1_wen;
	output							ssram1_cken;
	output							ssram1_adv;
	output							ssram1_oen;
	output							ssram1_csn;

	//	External SSRAM2 Port
	input							clk6p;
	output							pll6_out0;
	output							pll6_out1;
	input							pll6_fbin;
	output	[19:0]					ssram2_ab;
	inout	[35:0]					ssram2_db;
	output							ssram2_bwan;
	output							ssram2_bwbn;
	output							ssram2_bwcn;
	output							ssram2_bwdn;
	output							ssram2_wen;
	output							ssram2_cken;
	output							ssram2_adv;
	output							ssram2_oen;
	output							ssram2_csn;

	//	External I/O Port
		
	//	LED & 7SEG-LED
	output	[7:0]					seg_db;
	output	[3:0]					seg_sel;
	output	[7:0]					led;

	output							dummy;

	wire	[35:0]					lfsr1_wire, lfsr2_wire;
	wire	[2:0]					main1_state, main2_state;
	wire	[7:0]					count1, count2;
	wire	[31:0]					num1, num2;
	wire							start1, start2;
	wire							seg_clk;
	
	wire							write_enable1, write_enable2;
	wire	[35:0]					ssram1_q, ssram2_q;
	wire	[19:0]					int1_ab, int2_ab;
	wire							int1_csn, int2_csn;
	wire							int1_wen, int2_wen;
	wire							int1_gn, int2_gn;
	wire							int1_bwan, int2_bwan;
	wire							int1_bwbn, int2_bwbn;
	wire							int1_bwcn, int2_bwcn;
	wire							int1_bwdn, int2_bwdn;
	wire							int1_adv, int2_adv;

	/*	--------	PLL3 Declaration	--------	*/
	PLL3				pll3	(	.inclk0( clk48m_c ),
									.areset( !rstn ),
									.c0( seg_clk )
								);

	/*	--------	PLL5 Declaration	--------	*/
	PLL5				pll5	(	.inclk0( clk14p ),
									.areset( !rstn ),
									.c0( pll5_out0 ),
									.c1( pll5_out1 )
								);

	/*	--------	PLL6 Declaration	--------	*/
	PLL6				pll6	(	.inclk0( clk6p ),
									.areset( !rstn ),
									.c0( pll6_out0 ),
									.c1( pll6_out1 )
								);

	/*	--------	SSRAM1 controler Declaration	--------	*/
	SSRAM				ssram1	(	.clk( pll5_out0 ),
									.rstn( rstn ),
									.start( start1 ),
									.lfsr( lfsr1_wire ),
									.write_enable( write_enable1 ),
									.ssram_q( ssram1_q ),
									.ab( int1_ab ),
									.csn( int1_csn ),
									.wn( int1_wen ),
									.gn( int1_gn ),
									.bwan( int1_bwan ),
									.bwbn( int1_bwbn ),
									.bwcn( int1_bwcn ),
									.bwdn( int1_bwdn ),
									.adv( int1_adv ),
									.cken( ssram1_cken ),
									.main_state( main1_state ),
									.count( count1 )
								);

	/*	--------	SSRAM1 I/O Buffers Declaration	--------	*/
	//	SSRAM1 I/O DATA Buffers
	IO_Buffers			io_buf1		(	.clk( pll5_out0 ),
										.rstn( rstn ),
										.enable( write_enable1 ),
										.in( lfsr1_wire ),
										.q( ssram1_db )
									);

	defparam			in_buf11.WIDTH	=	36;
	IN_Buffers			in_buf11	(	.clk( pll5_out0 ),
										.rstn( rstn ),
										.d( ssram1_db ),
										.q( ssram1_q )
									);
									
	//	SSRAM1 I/O ADDRESS Buffers
	defparam			out_buf11.WIDTH	=	20;
	OUT_Buffers			out_buf11	(	.clk( pll5_out0 ),
										.rstn( rstn ),
										.d( int1_ab ),
										.q( ssram1_ab )
									);
	//	SSRAM1 I/O CSn Buffers
	defparam			out_buf12.WIDTH	=	1;
	OUT_Buffers			out_buf12	(	.clk( pll5_out0 ),
										.rstn( rstn ),
										.d( int1_csn ),
										.q( ssram1_csn )
									);
	//	SSRAM1 I/O Wn Buffers
	defparam			out_buf13.WIDTH	=	1;
	OUT_Buffers			out_buf13	(	.clk( pll5_out0 ),
										.rstn( rstn ),
										.d( int1_wen ),
										.q( ssram1_wen )
									);
	//	SSRAM1 I/O Gn Buffers
	defparam			out_buf14.WIDTH	=	1;
	OUT_Buffers			out_buf14	(	.clk( pll5_out0 ),
										.rstn( rstn ),
										.d( int1_gn ),
										.q( ssram1_oen )
									);
	//	SSRAM1 I/O BYTEn Buffers
	defparam			out_buf15.WIDTH	=	4;
	OUT_Buffers			out_buf15	(	.clk( pll5_out0 ),
										.rstn( rstn ),
										.d( { int1_bwan, int1_bwbn, int1_bwcn, int1_bwdn } ),
										.q( { ssram1_bwan, ssram1_bwbn, ssram1_bwcn, ssram1_bwdn } )
									);
	//	SSRAM1 I/O ADV Buffers
	defparam			out_buf16.WIDTH	=	1;
	OUT_Buffers			out_buf16	(	.clk( pll5_out0 ),
										.rstn( rstn ),
										.d( int1_adv ),
										.q( ssram1_adv )
									);

	/*	--------	SSRAM2 controler Declaration	--------	*/
	SSRAM				ssram2	(	.clk( pll6_out0 ),
									.rstn( rstn ),
									.start( start2 ),
									.lfsr( lfsr2_wire ),
									.write_enable( write_enable2 ),
									.ssram_q( ssram2_q ),
									.ab( int2_ab ),
									.csn( int2_csn ),
									.wn( int2_wen ),
									.gn( int2_gn ),
									.bwan( int2_bwan ),
									.bwbn( int2_bwbn ),
									.bwcn( int2_bwcn ),
									.bwdn( int2_bwdn ),
									.adv( int2_adv ),
									.cken( ssram2_cken ),
									.main_state( main2_state ),
									.count( count1 )
								);

	/*	--------	SSRAM2 I/O Buffers Declaration	--------	*/
	//	SSRAM2 I/O DATA Buffers
	IO_Buffers			io_buf2		(	.clk( pll6_out0 ),
										.rstn( rstn ),
										.enable( write_enable2 ),
										.in( lfsr2_wire ),
										.q( ssram2_db )
									);

	defparam			in_buf21.WIDTH	=	36;
	IN_Buffers			in_buf21	(	.clk( pll6_out0 ),
										.rstn( rstn ),
										.d( ssram2_db ),
										.q( ssram2_q )
									);
									
	//	SSRAM2 I/O ADDRESS Buffers
	defparam			out_buf21.WIDTH	=	20;
	OUT_Buffers			out_buf21	(	.clk( pll6_out0 ),
										.rstn( rstn ),
										.d( int2_ab ),
										.q( ssram2_ab )
									);
	//	SSRAM2 I/O CSn Buffers
	defparam			out_buf22.WIDTH	=	1;
	OUT_Buffers			out_buf22	(	.clk( pll6_out0 ),
										.rstn( rstn ),
										.d( int2_csn ),
										.q( ssram2_csn )
									);
	//	SSRAM2 I/O Wn Buffers
	defparam			out_buf23.WIDTH	=	1;
	OUT_Buffers			out_buf23	(	.clk( pll6_out0 ),
										.rstn( rstn ),
										.d( int2_wen ),
										.q( ssram2_wen )
									);
	//	SSRAM2 I/O Gn Buffers
	defparam			out_buf24.WIDTH	=	1;
	OUT_Buffers			out_buf24	(	.clk( pll6_out0 ),
										.rstn( rstn ),
										.d( int2_gn ),
										.q( ssram2_oen )
									);
	//	SSRAM2 I/O BYTEn Buffers
	defparam			out_buf25.WIDTH	=	4;
	OUT_Buffers			out_buf25	(	.clk( pll6_out0 ),
										.rstn( rstn ),
										.d( { int2_bwan, int2_bwbn, int2_bwcn, int2_bwdn } ),
										.q( { ssram2_bwan, ssram2_bwbn, ssram2_bwcn, ssram2_bwdn } )
									);
	//	SSRAM2 I/O ADV Buffers
	defparam			out_buf26.WIDTH	=	1;
	OUT_Buffers			out_buf26	(	.clk( pll6_out0 ),
										.rstn( rstn ),
										.d( int2_adv ),
										.q( ssram2_adv )
									);

	/*	--------	LFSR module Declaration	--------	*/
	LFSR				lfsr1		(	.clk( pll5_out0 ),
										.rstn( rstn ),
										.enable( 1'b1 ),
										.q( lfsr1_wire )
									);

	/*	--------	LFSR module Declaration	--------	*/
	LFSR				lfsr2		(	.clk( pll6_out0 ),
										.rstn( rstn ),
										.enable( 1'b1 ),
										.q( lfsr2_wire )
									);

	/*	--------	7Seg-LED Declaration		--------	*/
	DispCont			disp	(	.clk( seg_clk ),
									.rstn( rstn ),
									.dis( 1'b0 ),
									.data_in({ num2[10:3], num1[10:3] }),
									.matrix_db( seg_db ),
									.matrix_sel( seg_sel )
								);

	assign	led				=	~({ num2[1], main2_state, num1[1], main1_state });
	assign	dummy			=	pll5_fbin & pll6_fbin & rst1n;

	/*	--------	SSRAM1 Loop Counter Declaration		--------	*/
	LoopCnt				loop1	(	.clk( pll5_out0 ),
									.rstn( rstn ),
									.state( main1_state ),
									.ab( ssram1_ab ),
									.cnt( num1 )
								);

	/*	--------	SSRAM2 Loop Counter Declaration		--------	*/
	LoopCnt				loop2	(	.clk( pll6_out0 ),
									.rstn( rstn ),
									.state( main2_state ),
									.ab( ssram2_ab ),
									.cnt( num2 )
								);
	
	/*	--------	SSRAM1 Loop-Start Signal Declaration		--------	*/
	Delay				sdelay1	(	.clk( pll5_out0 ),
									.rstn( rstn ),
									.start( start1 )
								);

	/*	--------	SSRAM2 Loop-Start Signal Declaration		--------	*/
	Delay				sdelay2	(	.clk( pll6_out0 ),
									.rstn( rstn ),
									.start( start2 )
								);
	
endmodule