?? in_buffers.v
字號:
/* -------------------------------------------------------------
Synthesis & Fitter tool = "QuartusII5.0WE"
FileName = IN_Buffers.v
M.YOSHIDA 15.MAY.2005 REV 1.0
------------------------------------------------------------- */
// Module Declaration
module IN_Buffers ( clk, // Synchronous clock input
rstn, // Negative reset input
d, // Data input
q // Data output
);
parameter WIDTH = 8;
// port declaration
input clk, rstn;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
// reg & wire declaration
reg [WIDTH-1:0] q;
/* ------------ output declaration ------------ */
always @( posedge clk or negedge rstn ) begin
if( !rstn ) begin
// reset state
q <= 0;
end
else begin
// normal state
q <= d;
end
end
endmodule
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