/* -----------------------------------------------------------------
	Randam Pattern Generator		TAB = 4;
	Verilog-HDL Version

	Synthesis & Fitter tool = "QuartusII5.0WE"

	FileName = LFSR.v
	
	M.YOSHIDA				15.MAY.2005		REV	1.0
----------------------------------------------------------------- */
//	Define Declaration
//	Module Declaration
module	LFSR	(	clk,				//	System clock 48MHz input
					rstn,				//	Active low reset input
					enable,				//	
					q					//	
				);

	//	Parameter  Declaration
	//	Port declaration
	input							clk;
	input							rstn;
	input							enable;

	output	[35:0]					q;

	reg		[35:0]					q;
	wire							feedback;

	assign	feedback	=	q[35];
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn )	begin
			q	<=	35'h0_0000_0000;
		end
		else	begin
			if( enable )	begin
				q[0]	<=	feedback;
				q[1]	<=	q[0];
				q[2]	<=	q[1];
				q[3]	<=	q[2];
				q[4]	<=	q[3] ~^ feedback;
				q[5]	<=	q[4];
				q[6]	<=	q[5];
				q[7]	<=	q[6];
				q[8]	<=	q[7];
				q[9]	<=	q[8] ~^ feedback;
				q[10]	<=	q[9];
				q[11]	<=	q[10];
				q[12]	<=	q[11];
				q[13]	<=	q[12];
				q[14]	<=	q[13];
				q[15]	<=	q[14];
				q[16]	<=	q[15];
				q[17]	<=	q[16];
				q[18]	<=	q[17];
				q[19]	<=	q[18];
				q[20]	<=	q[19] ~^ feedback;
				q[21]	<=	q[20];
				q[22]	<=	q[21];
				q[23]	<=	q[22];
				q[24]	<=	q[23];
				q[25]	<=	q[24];
				q[26]	<=	q[25];
				q[27]	<=	q[26];
				q[28]	<=	q[27];
				q[29]	<=	q[28];
				q[30]	<=	q[29];
				q[31]	<=	q[30];
				q[32]	<=	q[31];
				q[33]	<=	q[32] ~^ feedback;
				q[34]	<=	q[33];
				q[35]	<=	q[34];
			end
			else	begin
				q		<=	q;
			end
		end
	end
endmodule