; Total number of failed paths ;                                          ;               ;                                  ;                      ;                      ;            ;          ; 6            ;
+------------------------------+------------------------------------------+---------------+----------------------------------+----------------------+----------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K30QC208-3      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; pin_clk         ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pin_clk'                                                                                                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                  ; To                                                                    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 101.01 MHz ( period = 9.900 ns )                    ; light:inst1|flag[2]                                                   ; light:inst1|light[5]                                                  ; pin_clk    ; pin_clk  ; None                        ; None                      ; 7.700 ns                ;
; N/A                                     ; 102.04 MHz ( period = 9.800 ns )                    ; light:inst1|flag[0]                                                   ; light:inst1|light[5]                                                  ; pin_clk    ; pin_clk  ; None                        ; None                      ; 7.700 ns                ;
; N/A                                     ; 103.09 MHz ( period = 9.700 ns )                    ; light:inst1|flag[1]                                                   ; light:inst1|light[5]                                                  ; pin_clk    ; pin_clk  ; None                        ; None                      ; 7.600 ns                ;
; N/A                                     ; 112.36 MHz ( period = 8.900 ns )                    ; light:inst1|flag[1]                                                   ; light:inst1|light[6]                                                  ; pin_clk    ; pin_clk  ; None                        ; None                      ; 6.800 ns                ;
; N/A                                     ; 112.36 MHz ( period = 8.900 ns )                    ; light:inst1|flag[0]                                                   ; light:inst1|light[6]                                                  ; pin_clk    ; pin_clk  ; None                        ; None                      ; 6.800 ns                ;
; N/A                                     ; 116.28 MHz ( period = 8.600 ns )                    ; light:inst1|flag[1]                                                   ; light:inst1|light[2]                                                  ; pin_clk    ; pin_clk  ; None                        ; None                      ; 7.200 ns                ;
; N/A                                     ; 116.28 MHz ( period = 8.600 ns )                    ; light:inst1|flag[1]                                                   ; light:inst1|light[1]                                                  ; pin_clk    ; pin_clk  ; None                        ; None                      ; 7.200 ns                ;