library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity divid is
port (testin:in std_logic_vector(4 downto 0);
      datain:in std_logic_vector(7 downto 0);
      testout0:out std_logic;
      testout1:out std_logic;
      testout2:out std_logic;
      testout3:out std_logic;
      testout4:out std_logic;
      dataout0:out std_logic;
      dataout1:out std_logic;
      dataout2:out std_logic;
      dataout3:out std_logic;
      dataout4:out std_logic;
      dataout5:out std_logic;
      dataout6:out std_logic;
      dataout7:out std_logic);
end divid;
architecture beta of divid is
begin
  testout0<=testin(0);
  testout1<=testin(1);
  testout2<=testin(2);
  testout3<=testin(3);
  testout4<=testin(4);
  dataout0<=datain(0);
  dataout1<=datain(1);
  dataout2<=datain(2);
  dataout3<=datain(3);
  dataout4<=datain(4);
  dataout5<=datain(5);
  dataout6<=datain(6);
  dataout7<=datain(7);
end architecture;