################################################################################# Actual Synthesis Script## This script does the actual synthesis## Author: Rudolf Usselmann#         rudi@asics.ws## Revision:# 3/7/01 RU Initial Sript################################################################################## ==============================================# Setup Design Parameterssource ../bin/design_spec_po.dc# ==============================================# Setup Librariessource ../bin/lib_spec.dc# ==============================================# Setup IO Filesappend log_file			../log/$active_design "_cmp.log"append pre_comp_db_file		../out/$design_name "_pre.db"append post_comp_db_file	../out/$design_name ".db"append post_syn_verilog_file	../out/$design_name "_ps.v"set junk_file /dev/nullsh rm -f $log_file# ==============================================# Setup Misc Variablesset hdlin_enable_vpp true       ;# Important - this enables 'ifdefs# ==============================================# Read Designecho "+++++++++ Reading Design ..."                             >> $log_fileread_file $pre_comp_db_file                                     >> $log_file# ==============================================# Operating conditionsecho "+++++++++ Setting up Operation Conditions ..."            >> $log_filecurrent_design $design_nameset_operating_conditions WORST                                  >> $log_file# ==============================================# Setup Clocks and Resetsecho "+++++++++ Setting up Clocks ..."                           >> $log_fileset_drive 0 [find port {*clk*}] set wb_clk_period 3.0create_clock clk -period $wb_clk_period set_clock_skew -uncertainty 0.1 clkset_clock_transition 0.2 clkset_dont_touch_network clk # ==============================================# Setup IOsecho "+++++++++ Setting up IOs ..."                             >> $log_file# Need to spell out external IOsset_driving_cell -cell NAND2D2 -pin Z [all_inputs]              >> $junk_fileset_load 0.2 [all_outputs]set_input_delay 2.0 -clock clk [all_inputs]set_output_delay 2.0 -clock clk [all_outputs]# ==============================================# Specify Multi Cycle Paths# ==============================================# Setup Area Constrainsset_max_area 0.0set compile_sequential_area_recovery true# ==============================================# Force Ultraset_ultra_optimization -fset_balance_registers true# ==============================================# Compile Designecho "+++++++++ Starting Compile ..."                           >> $log_fileungroup -all -flatten						>> $log_filecompile								>> $log_fileoptimize_registers -period 0					>> $log_file#compile -incremental_mapping -map_effort high -area_effort high -boundary_optimization -ungroup_all	>> $log_file#compile -map_effort high -area_effort high -boundary_optimization -auto_ungroup	>> $log_file# ==============================================# Write Out the optimized designecho "+++++++++ Saving Optimized Design ..."                    >> $log_filewrite_file -hierarchy -format verilog -output $post_syn_verilog_filewrite_file -hierarchy -format db      -output $post_comp_db_file# ==============================================# Create Some Basic Reportsecho "+++++++++ Reporting Final Results ..."                    >> $log_filereport_timing -nworst 10                                        >> $log_filereport_area                                                     >> $log_file