?? example6-8.vhd
字號:
LIBRARY IEEE;
ENTITY test IS END;
ARCHITECTURE example OF test IS
SIGNAL s : INTEGER := 0;
BEGIN
PROCESS
BEGIN
s <= REJECT 5ns INERTIAL 3 AFTER 1ns, 5 AFTER 3ns,
6 AFTER 5ns, 8 AFTER 6ns, 6 AFTER 8ns, 7 AFTER 15ns;
s <= REJECT 5ns INERTIAL 6 AFTER 9ns, 10 AFTER 18ns;
WAIT;
END PROCESS;
END example;
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