--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--associated documentation or information provided by Altera or a partner
--under Altera's Megafunction Partnership Program may be used only to
--program PLD devices (but not masked PLD devices) from Altera.  Any other
--use of such megafunction design, net list, support information, device
--programming or simulation file, or any other related documentation or
--information is prohibited for any other purpose, including, but not
--limited to modification, reverse engineering, de-compiling, or use with
--any other silicon devices, unless such use is explicitly licensed under
--a separate agreement with Altera or a megafunction partner.  Title to
--the intellectual property, including patents, copyrights, trademarks,
--trade secrets, or maskworks, embodied in any such megafunction design,
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--any other related documentation or information provided by Altera or a
--megafunction partner, remains with Altera, the megafunction partner, or
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--needed under any third party's intellectual property, are provided herein.
--Copying or modifying any file, or portion thereof, to which this notice
--is attached violates this copyright.

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity CPU_opcode_display_unit is 
        port (
              -- inputs:
                 signal instruction : IN STD_LOGIC_VECTOR (15 DOWNTO 0)
              );
end entity CPU_opcode_display_unit;


architecture europa of CPU_opcode_display_unit is
                signal opcode :  STD_LOGIC_VECTOR (6 DOWNTO 0);

begin

--exemplar translate_off
    opcode <= A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND NOT instruction(13)) AND NOT instruction(12)) AND NOT instruction(11)) AND NOT instruction(10)))) = '1'), "0000000", A_WE_StdLogicVector((std_logic'(((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND NOT instruction(11)) AND instruction(10))) AND NOT instruction(9)) AND NOT instruction(8)) AND NOT instruction(7)))) = '1'), "0000001", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND NOT instruction(13)) AND NOT instruction(12)) AND NOT instruction(11)) AND instruction(10)))) = '1'), "0000010", A_WE_StdLogicVector((std_logic'(((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND NOT instruction(11)) AND instruction(10))) AND NOT instruction(9)) AND NOT instruction(8)) AND instruction(7)))) = '1'), "0000011", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND NOT instruction(13)) AND NOT instruction(12)) AND instruction(11)) AND NOT instruction(10)))) = '1'), "0000100", A_WE_StdLogicVector((std_logic'(((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND NOT instruction(11)) AND instruction(10))) AND instruction(9)) AND NOT instruction(8)) AND NOT instruction(7)))) = '1'), "0000101", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND NOT instruction(13)) AND NOT instruction(12)) AND instruction(11)) AND instruction(10)))) = '1'), "0000110", A_WE_StdLogicVector((std_logic'(((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND NOT instruction(11)) AND instruction(10))) AND instruction(9)) AND NOT instruction(8)) AND instruction(7)))) = '1'), "0000111", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND NOT instruction(13)) AND instruction(12)) AND NOT instruction(11)) AND NOT instruction(10)))) = '1'), "0001000", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND NOT instruction(13)) AND instruction(12)) AND NOT instruction(11)) AND instruction(10)))) = '1'), "0001001", A_WE_StdLogicVector((std_logic'((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND NOT instruction(10))) AND NOT instruction(9)) AND NOT instruction(8)))) = '1'), "0001010", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND NOT instruction(13)) AND instruction(12)) AND instruction(11)) AND NOT instruction(10)))) = '1'), "0001011", A_WE_StdLogicVector((std_logic'((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND NOT instruction(10))) AND NOT instruction(9)) AND instruction(8)))) = '1'), "0001100", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND NOT instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10)))) = '1'), "0001101", A_WE_StdLogicVector((std_logic'((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND NOT instruction(10))) AND instruction(9)) AND NOT instruction(8)))) = '1'), "0001110", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND instruction(13)) AND NOT instruction(12)) AND NOT instruction(11)) AND NOT instruction(10)))) = '1'), "0001111", A_WE_StdLogicVector((std_logic'((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND NOT instruction(10))) AND instruction(9)) AND instruction(8)))) = '1'), "0010000", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND instruction(13)) AND NOT instruction(12)) AND NOT instruction(11)) AND instruction(10)))) = '1'), "0010001", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND instruction(13)) AND NOT instruction(12)) AND instruction(11)) AND NOT instruction(10)))) = '1'), "0010010", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND NOT instruction(9)) AND NOT instruction(8)) AND NOT instruction(7)) AND NOT instruction(6)) AND NOT instruction(5)))) = '1'), "0010011", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND instruction(13)) AND NOT instruction(12)) AND instruction(11)) AND instruction(10)))) = '1'), "0010100", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND NOT instruction(9)) AND NOT instruction(8)) AND NOT instruction(7)) AND NOT instruction(6)) AND instruction(5)))) = '1'), "0010101", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND instruction(13)) AND instruction(12)) AND NOT instruction(11)) AND NOT instruction(10)))) = '1'), "0010110", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND NOT instruction(9)) AND NOT instruction(8)) AND NOT instruction(7)) AND instruction(6)) AND NOT instruction(5)))) = '1'), "0010111", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND instruction(13)) AND instruction(12)) AND NOT instruction(11)) AND instruction(10)))) = '1'), "0011000", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND NOT instruction(9)) AND NOT instruction(8)) AND NOT instruction(7)) AND instruction(6)) AND instruction(5)))) = '1'), "0011001", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND NOT instruction(10)))) = '1'), "0011010", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND NOT instruction(9)) AND NOT instruction(8)) AND instruction(7)) AND NOT instruction(6)) AND NOT instruction(5)))) = '1'), "0011011", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND NOT instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10)))) = '1'), "0011100", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND NOT instruction(9)) AND NOT instruction(8)) AND instruction(7)) AND NOT instruction(6)) AND instruction(5)))) = '1'), "0011101", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND instruction(14)) AND NOT instruction(13)) AND NOT instruction(12)) AND NOT instruction(11)) AND NOT instruction(10)))) = '1'), "0011110", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND NOT instruction(9)) AND NOT instruction(8)) AND instruction(7)) AND instruction(6)) AND NOT instruction(5)))) = '1'), "0011111", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND instruction(14)) AND NOT instruction(13)) AND NOT instruction(12)) AND NOT instruction(11)) AND instruction(10)))) = '1'), "0100000", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND instruction(14)) AND NOT instruction(13)) AND NOT instruction(12)) AND instruction(11)) AND NOT instruction(10)))) = '1'), "0100001", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND NOT instruction(9)) AND instruction(8)) AND NOT instruction(7)) AND NOT instruction(6)) AND NOT instruction(5)))) = '1'), "0100010", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND instruction(14)) AND NOT instruction(13)) AND NOT instruction(12)) AND instruction(11)) AND instruction(10)))) = '1'), "0100011", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND instruction(14)) AND NOT instruction(13)) AND instruction(12)) AND NOT instruction(11)) AND NOT instruction(10)))) = '1'), "0100100", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND instruction(14)) AND NOT instruction(13)) AND instruction(12)) AND NOT instruction(11)) AND instruction(10)))) = '1'), "0100101", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND instruction(14)) AND NOT instruction(13)) AND instruction(12)) AND instruction(11)) AND NOT instruction(10)))) = '1'), "0100110", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND instruction(14)) AND NOT instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10)))) = '1'), "0100111", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND NOT instruction(12)) AND NOT instruction(11)) AND NOT instruction(10)))) = '1'), "0101000", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND NOT instruction(12)) AND NOT instruction(11)) AND instruction(10)))) = '1'), "0101001", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND NOT instruction(9)) AND instruction(8)) AND instruction(7)) AND NOT instruction(6)) AND instruction(5)))) = '1'), "0101010", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND NOT instruction(9)) AND instruction(8)) AND instruction(7)) AND instruction(6)) AND NOT instruction(5)))) = '1'), "0101011", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND instruction(9)) AND NOT instruction(8)) AND NOT instruction(7)) AND NOT instruction(6)) AND NOT instruction(5)))) = '1'), "0101100", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND NOT instruction(12)) AND instruction(11)) AND NOT instruction(10)))) = '1'), "0101101", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND instruction(9)) AND NOT instruction(8)) AND NOT instruction(7)) AND NOT instruction(6)) AND instruction(5)))) = '1'), "0101110", A_WE_StdLogicVector((std_logic'(((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND NOT instruction(12)) AND instruction(11)) AND instruction(10)))) = '1'), "0101111", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND instruction(9)) AND NOT instruction(8)) AND NOT instruction(7)) AND instruction(6)) AND NOT instruction(5)))) = '1'), "0110000", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND instruction(9)) AND NOT instruction(8)) AND NOT instruction(7)) AND instruction(6)) AND instruction(5)))) = '1'), "0110001", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND instruction(9)) AND NOT instruction(8)) AND instruction(7)) AND NOT instruction(6)) AND NOT instruction(5)))) = '1'), "0110010", A_WE_StdLogicVector((std_logic'((((((instruction(15) AND NOT instruction(14)) AND NOT instruction(13)) AND NOT instruction(12)) AND NOT instruction(11)))) = '1'), "0110011", A_WE_StdLogicVector((std_logic'((((((instruction(15) AND NOT instruction(14)) AND NOT instruction(13)) AND NOT instruction(12)) AND instruction(11)))) = '1'), "0110100", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND instruction(9)) AND NOT instruction(8)) AND instruction(7)) AND instruction(6)) AND NOT instruction(5)))) = '1'), "0110101", A_WE_StdLogicVector((std_logic'((((((instruction(15) AND NOT instruction(14)) AND NOT instruction(13)) AND instruction(12)) AND NOT instruction(11)))) = '1'), "0110110", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND instruction(9)) AND NOT instruction(8)) AND instruction(7)) AND instruction(6)) AND instruction(5)))) = '1'), "0110111", A_WE_StdLogicVector((std_logic'((((((instruction(15) AND NOT instruction(14)) AND NOT instruction(13)) AND instruction(12)) AND instruction(11)))) = '1'), "0111000", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND instruction(9)) AND instruction(8)) AND NOT instruction(7)) AND NOT instruction(6)) AND NOT instruction(5)))) = '1'), "0111001", A_WE_StdLogicVector((std_logic'(((((instruction(15) AND NOT instruction(14)) AND instruction(13)) AND NOT instruction(12)))) = '1'), "0111010", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND instruction(9)) AND instruction(8)) AND NOT instruction(7)) AND NOT instruction(6)) AND instruction(5)))) = '1'), "0111011", A_WE_StdLogicVector((std_logic'(((((instruction(15) AND NOT instruction(14)) AND instruction(13)) AND instruction(12)))) = '1'), "0111100", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND instruction(9)) AND instruction(8)) AND NOT instruction(7)) AND instruction(6)) AND NOT instruction(5)))) = '1'), "0111101", A_WE_StdLogicVector((std_logic'((((instruction(15) AND instruction(14)) AND NOT instruction(13)))) = '1'), "0111110", A_WE_StdLogicVector((std_logic'(((((((((((((NOT instruction(15) AND instruction(14)) AND instruction(13)) AND instruction(12)) AND instruction(11)) AND instruction(10))) AND instruction(9)) AND instruction(8)) AND instruction(7)) AND instruction(6)) AND NOT instruction(5)))) = '1'), "0111111", A_WE_StdLogicVector((std_logic'((((instruction(15) AND instruction(14)) AND instruction(13)))) = '1'), "1000000", "1000001")))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))));
--exemplar translate_on

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity CPU_interrupt_control is 
        port (
              -- inputs:
                 signal IE : IN STD_LOGIC;
                 signal IPRI : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                 signal cancel_branch_delay_slot : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal do_not_interrupt : IN STD_LOGIC;
                 signal instruction_1 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal irq : IN STD_LOGIC;
                 signal irqnumber : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                 signal is_cancelled : IN STD_LOGIC;
                 signal is_cancelled_from_commit_stage : IN STD_LOGIC;
                 signal is_neutrino : IN STD_LOGIC;
                 signal op_is_trap : IN STD_LOGIC;
                 signal pipe_run : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal subinstruction : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal trap_request_overflow : IN STD_LOGIC;
                 signal trap_request_underflow : IN STD_LOGIC;

              -- outputs:
                 signal do_cancel_next_instruction : OUT STD_LOGIC;
                 signal do_force_trap : OUT STD_LOGIC;
                 signal forced_trap_instruction : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal trap_properly_received : OUT STD_LOGIC
              );
end entity CPU_interrupt_control;


architecture europa of CPU_interrupt_control is
                signal already_processing_trap :  STD_LOGIC;
                signal d1_irq :  STD_LOGIC;
                signal d1_irqnumber :  STD_LOGIC_VECTOR (5 DOWNTO 0);
                signal d2_irq :  STD_LOGIC;
                signal d2_irqnumber :  STD_LOGIC_VECTOR (5 DOWNTO 0);
                signal dont_forget_im_processing_a_trap :  STD_LOGIC;
                signal forced_trap_number :  STD_LOGIC_VECTOR (5 DOWNTO 0);
                signal instruction :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal internal_do_force_trap :  STD_LOGIC;
                signal internal_trap_properly_received :  STD_LOGIC;
                signal interrupt_pending :  STD_LOGIC;
                signal interruptable_instruction :  STD_LOGIC;
                signal local_pipe_clk_en :  STD_LOGIC;
                signal oci_irq :  STD_LOGIC;
                signal pipe_state_we :  STD_LOGIC;
                signal trap_ok :  STD_LOGIC;
                signal trap_request :  STD_LOGIC;

begin

  instruction <= instruction_1;
  local_pipe_clk_en <= pipe_run;
  pipe_state_we <= (local_pipe_clk_en AND NOT is_neutrino) AND NOT is_cancelled;
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_irqnumber <= "000000";
    elsif clk'event and clk = '1' then
      if true then 
        d1_irqnumber <= irqnumber AND NOT (A_REP(oci_irq, 6));
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d2_irqnumber <= "000000";
    elsif clk'event and clk = '1' then
      if true then 
        d2_irqnumber <= d1_irqnumber;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_irq <= '0';
    elsif clk'event and clk = '1' then
      if true then 
        d1_irq <= irq OR oci_irq;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d2_irq <= '0';
    elsif clk'event and clk = '1' then
      if true then 
        d2_irq <= d1_irq AND to_std_logic(((d1_irqnumber<IPRI)));
      end if;
    end if;

  end process;

  oci_irq <= '0';
  trap_request <= (d2_irq OR trap_request_underflow) OR trap_request_overflow;
  internal_do_force_trap <= trap_request AND trap_ok;
  forced_trap_number <= A_WE_StdLogicVector((std_logic'((trap_request_underflow)) = '1'), "000001", A_WE_StdLogicVector((std_logic'((trap_request_overflow)) = '1'), "000010", d2_irqnumber));
  forced_trap_instruction <= (Std_Logic_Vector'("011110" & "0000000000") OR Std_Logic_Vector'("000000" & "01" & "00000000")) OR Std_Logic_Vector'("0000000000" & forced_trap_number);
  trap_ok <= ((interruptable_instruction AND NOT already_processing_trap) AND NOT interrupt_pending) AND ((IE OR ('0')));
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      interrupt_pending <= '0';
    elsif clk'event and clk = '1' then
      if std_logic'(local_pipe_clk_en) = '1' then 
        if std_logic'(internal_trap_properly_received) = '1' then 
          interrupt_pending <= '0';
        elsif std_logic'(internal_do_force_trap) = '1' then 
          interrupt_pending <= '1';
        end if;
      end if;
    end if;

  end process;

  internal_trap_properly_received <= ((op_is_trap) AND (NOT is_neutrino)) AND (NOT is_cancelled_from_commit_stage);
  interruptable_instruction <= ((trap_request_underflow) OR (trap_request_overflow)) OR (((((NOT do_not_interrupt) AND (NOT or_reduce(subinstruction))) AND (NOT is_neutrino)) AND (NOT is_cancelled_from_commit_stage)));
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      dont_forget_im_processing_a_trap <= '0';
    elsif clk'event and clk = '1' then
      if std_logic'(pipe_state_we) = '1' then 
        if std_logic'(op_is_trap) = '1' then 
          dont_forget_im_processing_a_trap <= '1';
        elsif true then 
          dont_forget_im_processing_a_trap <= '0';
        end if;
      end if;
    end if;

  end process;

  already_processing_trap <= (((op_is_trap AND NOT is_neutrino) AND NOT is_cancelled_from_commit_stage)) OR (dont_forget_im_processing_a_trap);
  do_cancel_next_instruction <= (cancel_branch_delay_slot AND NOT is_cancelled) AND NOT is_neutrino;
  --vhdl renameroo for output signals
  do_force_trap <= internal_do_force_trap;
  --vhdl renameroo for output signals
  trap_properly_received <= internal_trap_properly_received;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity CPU_address_request is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal d1_instruction_fifo_read_data_bad : IN STD_LOGIC;
                 signal do_branch : IN STD_LOGIC;