signal do_jump : IN STD_LOGIC;
                 signal ic_read : IN STD_LOGIC;
                 signal ic_wait : IN STD_LOGIC;
                 signal instruction_fifo_read_data_bad : IN STD_LOGIC;
                 signal pipe_run : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal target_address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);

              -- outputs:
                 signal ic_flush : OUT STD_LOGIC;
                 signal p1_flush : OUT STD_LOGIC;
                 signal pc : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
              );
end entity CPU_address_request;


architecture europa of CPU_address_request is
                signal internal_p1_flush1 :  STD_LOGIC;
                signal internal_pc :  STD_LOGIC_VECTOR (11 DOWNTO 0);
                signal next_pc :  STD_LOGIC_VECTOR (11 DOWNTO 0);
                signal next_pc_plus_one :  STD_LOGIC_VECTOR (11 DOWNTO 0);
                signal nonsequential_pc :  STD_LOGIC;
                signal pc_clken :  STD_LOGIC;
                signal remember_to_flush :  STD_LOGIC;
                signal waiting_for_delay_slot :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_pc <= "100000000000";
    elsif clk'event and clk = '1' then
      if std_logic'(pc_clken) = '1' then 
        internal_pc <= next_pc;
      end if;
    end if;

  end process;

  next_pc_plus_one <= A_EXT ((("0" & (internal_pc)) + "0000000000001"), 12);
  pc_clken <= ((ic_read OR internal_p1_flush1)) AND NOT ic_wait;
  next_pc <= A_WE_StdLogicVector((std_logic'((((do_jump OR do_branch) OR ((remember_to_flush AND NOT waiting_for_delay_slot))))) = '1'), target_address, next_pc_plus_one);
  nonsequential_pc <= ((do_branch OR do_jump)) AND pipe_run;
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      ic_flush <= '0';
    elsif clk'event and clk = '1' then
      if std_logic'(NOT ic_wait) = '1' then 
        ic_flush <= internal_p1_flush1;
      end if;
    end if;

  end process;

  internal_p1_flush1 <= ((nonsequential_pc AND NOT d1_instruction_fifo_read_data_bad)) OR ((remember_to_flush AND NOT waiting_for_delay_slot));
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      remember_to_flush <= '0';
    elsif clk'event and clk = '1' then
      if true then 
        if std_logic'((internal_p1_flush1 AND NOT ic_wait)) = '1' then 
          remember_to_flush <= '0';
        elsif std_logic'((nonsequential_pc AND ((d1_instruction_fifo_read_data_bad OR ic_wait)))) = '1' then 
          remember_to_flush <= '1';
        end if;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      waiting_for_delay_slot <= '0';
    elsif clk'event and clk = '1' then
      if std_logic'(pipe_run) = '1' then 
        if std_logic'(NOT instruction_fifo_read_data_bad) = '1' then 
          waiting_for_delay_slot <= '0';
        elsif std_logic'((nonsequential_pc AND d1_instruction_fifo_read_data_bad)) = '1' then 
          waiting_for_delay_slot <= '1';
        end if;
      end if;
    end if;

  end process;

  --vhdl renameroo for output signals
  p1_flush <= internal_p1_flush1;
  --vhdl renameroo for output signals
  pc <= internal_pc;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity CPU_target_address is 
        port (
              -- inputs:
                 signal branch_base : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal do_branch : IN STD_LOGIC;
                 signal do_jump : IN STD_LOGIC;
                 signal jump_target_address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
                 signal pipe_run : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal signed_branch_offset : IN STD_LOGIC_VECTOR (11 DOWNTO 0);

              -- outputs:
                 signal target_address : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
              );
end entity CPU_target_address;


architecture europa of CPU_target_address is
                signal branch_target_address :  STD_LOGIC_VECTOR (11 DOWNTO 0);
                signal current_target_address :  STD_LOGIC_VECTOR (11 DOWNTO 0);
                signal last_target_address :  STD_LOGIC_VECTOR (11 DOWNTO 0);

begin

  branch_target_address <= A_EXT ((("0" & (branch_base)) + ("0" & (signed_branch_offset))), 12);
  current_target_address <= A_WE_StdLogicVector((std_logic'(do_jump) = '1'), jump_target_address, branch_target_address);
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      last_target_address <= "000000000000";
    elsif clk'event and clk = '1' then
      if std_logic'((pipe_run AND ((do_jump OR do_branch)))) = '1' then 
        last_target_address <= current_target_address;
      end if;
    end if;

  end process;

  target_address <= A_WE_StdLogicVector((std_logic'(((do_jump OR do_branch))) = '1'), current_target_address, last_target_address);

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity CPU_instruction_fetch is 
        port (
              -- inputs:
                 signal branch_base : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal d1_instruction_fifo_read_data_bad : IN STD_LOGIC;
                 signal do_branch : IN STD_LOGIC;
                 signal do_jump : IN STD_LOGIC;
                 signal ic_read : IN STD_LOGIC;
                 signal ic_wait : IN STD_LOGIC;
                 signal instruction_fifo_read_data_bad : IN STD_LOGIC;
                 signal jump_target_address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
                 signal pipe_run : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal signed_branch_offset : IN STD_LOGIC_VECTOR (11 DOWNTO 0);

              -- outputs:
                 signal ic_address : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
                 signal ic_flush : OUT STD_LOGIC;
                 signal p1_flush : OUT STD_LOGIC;
                 signal target_address : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of CPU_instruction_fetch : entity is FALSE;
end entity CPU_instruction_fetch;


architecture europa of CPU_instruction_fetch is
component CPU_address_request is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal d1_instruction_fifo_read_data_bad : IN STD_LOGIC;
                    signal do_branch : IN STD_LOGIC;
                    signal do_jump : IN STD_LOGIC;
                    signal ic_read : IN STD_LOGIC;
                    signal ic_wait : IN STD_LOGIC;
                    signal instruction_fifo_read_data_bad : IN STD_LOGIC;
                    signal pipe_run : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal target_address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);

                 -- outputs:
                    signal ic_flush : OUT STD_LOGIC;
                    signal p1_flush : OUT STD_LOGIC;
                    signal pc : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
                 );
end component CPU_address_request;

component CPU_target_address is 
           port (
                 -- inputs:
                    signal branch_base : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal do_branch : IN STD_LOGIC;
                    signal do_jump : IN STD_LOGIC;
                    signal jump_target_address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
                    signal pipe_run : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal signed_branch_offset : IN STD_LOGIC_VECTOR (11 DOWNTO 0);

                 -- outputs:
                    signal target_address : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
                 );
end component CPU_target_address;

                signal internal_ic_flush2 :  STD_LOGIC;