unxshiftxread_pointerxxrdaddress_calculatorx0_in <= A_WE_StdLogicVector((std_logic'((flush)) = '1'), "01", A_WE_StdLogicVector((std_logic'((fifo_dec)) = '1'), Std_Logic_Vector'(A_ToStdLogicVector(unxshiftxread_pointerxxrdaddress_calculatorx0_out(0)) & A_ToStdLogicVector(read_pointer(1))), unxshiftxread_pointerxxrdaddress_calculatorx0_out));
  read_pointer <= unxshiftxread_pointerxxrdaddress_calculatorx0_out;
  --wraddress_calculator_reg, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      unxshiftxwrite_pointerxxwraddress_calculatorx1_out <= "01";
    elsif clk'event and clk = '1' then
      if std_logic'(clk_en) = '1' then 
        unxshiftxwrite_pointerxxwraddress_calculatorx1_out <= unxshiftxwrite_pointerxxwraddress_calculatorx1_in;
      end if;
    end if;

  end process;

  unxshiftxwrite_pointerxxwraddress_calculatorx1_in <= A_WE_StdLogicVector((std_logic'((flush)) = '1'), "01", A_WE_StdLogicVector((std_logic'((fifo_inc)) = '1'), Std_Logic_Vector'(A_ToStdLogicVector(unxshiftxwrite_pointerxxwraddress_calculatorx1_out(0)) & A_ToStdLogicVector(write_pointer(1))), unxshiftxwrite_pointerxxwraddress_calculatorx1_out));
  write_pointer <= unxshiftxwrite_pointerxxwraddress_calculatorx1_out;
  --vhdl renameroo for output signals
  fifo_read_data_bad <= internal_fifo_read_data_bad;
  --vhdl renameroo for output signals
  ic_read <= internal_ic_read3;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity CPU_instruction_receive is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal commit : IN STD_LOGIC;
                 signal do_branch : IN STD_LOGIC;
                 signal do_force_trap : IN STD_LOGIC;
                 signal do_jump : IN STD_LOGIC;
                 signal feed_new_instruction : IN STD_LOGIC;
                 signal forced_trap_instruction : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal ic_datavalid : IN STD_LOGIC;
                 signal ic_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal ic_wait : IN STD_LOGIC;
                 signal is_subinstruction : IN STD_LOGIC;
                 signal p1_flush : IN STD_LOGIC;
                 signal pipe_freeze : IN STD_LOGIC;
                 signal pipe_run : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal target_address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
                 signal trap_properly_received : IN STD_LOGIC;

              -- outputs:
                 signal d1_instruction_fifo_out : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal d1_instruction_fifo_read_data_bad : OUT STD_LOGIC;
                 signal force_trap_acknowledge : OUT STD_LOGIC;
                 signal ic_read : OUT STD_LOGIC;
                 signal instruction : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal instruction_fifo_read_data_bad : OUT STD_LOGIC;
                 signal next_instruction_address : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of CPU_instruction_receive : entity is FALSE;
end entity CPU_instruction_receive;


architecture europa of CPU_instruction_receive is
component CPU_cpu_instruction_fifo_fifo_module is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clk_en : IN STD_LOGIC;
                    signal fifo_read : IN STD_LOGIC;
                    signal fifo_wr_data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal fifo_write : IN STD_LOGIC;
                    signal flush : IN STD_LOGIC;
                    signal ic_wait : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal fifo_rd_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal fifo_read_data_bad : OUT STD_LOGIC;
                    signal ic_read : OUT STD_LOGIC
                 );
end component CPU_cpu_instruction_fifo_fifo_module;

                signal dont_forget_to_force_trap :  STD_LOGIC;
                signal instruction_fifo_out :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal instruction_fifo_read :  STD_LOGIC;
                signal internal_d1_instruction_fifo_out :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal internal_d1_instruction_fifo_read_data_bad :  STD_LOGIC;
                signal internal_force_trap_acknowledge :  STD_LOGIC;
                signal internal_ic_read2 :  STD_LOGIC;
                signal internal_instruction_fifo_read_data_bad :  STD_LOGIC;
                signal internal_next_instruction_address1 :  STD_LOGIC_VECTOR (11 DOWNTO 0);
                signal next_instruction_address_enable :  STD_LOGIC;
                signal p1_next_instruction_address :  STD_LOGIC_VECTOR (11 DOWNTO 0);
                signal use_saved_next_address :  STD_LOGIC;

begin

  the_CPU_cpu_instruction_fifo_fifo_module : CPU_cpu_instruction_fifo_fifo_module
    port map(
      fifo_rd_data => instruction_fifo_out,
      fifo_read_data_bad => internal_instruction_fifo_read_data_bad,
      ic_read => internal_ic_read2,
      clk => clk,
      clk_en => '1',
      fifo_read => instruction_fifo_read,
      fifo_wr_data => ic_readdata,
      fifo_write => ic_datavalid,
      flush => p1_flush,
      ic_wait => ic_wait,
      reset_n => reset_n
    );


  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_d1_instruction_fifo_read_data_bad <= '1';
    elsif clk'event and clk = '1' then
      if std_logic'(instruction_fifo_read) = '1' then 
        internal_d1_instruction_fifo_read_data_bad <= (internal_instruction_fifo_read_data_bad) OR p1_flush;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_d1_instruction_fifo_out <= "0000000000000000";
    elsif clk'event and clk = '1' then
      if std_logic'(instruction_fifo_read) = '1' then 
        internal_d1_instruction_fifo_out <= instruction_fifo_out;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      dont_forget_to_force_trap <= '0';
    elsif clk'event and clk = '1' then
      if std_logic'(pipe_run) = '1' then 
        if std_logic'(trap_properly_received) = '1' then 
          dont_forget_to_force_trap <= '0';
        elsif std_logic'(do_force_trap) = '1' then 
          dont_forget_to_force_trap <= '1';
        end if;
      end if;
    end if;

  end process;

  internal_force_trap_acknowledge <= dont_forget_to_force_trap;
  instruction <= A_WE_StdLogicVector((std_logic'(internal_force_trap_acknowledge) = '1'), forced_trap_instruction, internal_d1_instruction_fifo_out);
  instruction_fifo_read <= commit OR ((internal_d1_instruction_fifo_read_data_bad AND NOT pipe_freeze));
  next_instruction_address_enable <= ((((feed_new_instruction) AND (NOT is_subinstruction)) AND (NOT pipe_freeze)) AND (NOT internal_d1_instruction_fifo_read_data_bad)) AND (NOT internal_force_trap_acknowledge);
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_next_instruction_address1 <= "100000000000";
    elsif clk'event and clk = '1' then
      if std_logic'(next_instruction_address_enable) = '1' then 
        internal_next_instruction_address1 <= p1_next_instruction_address;
      end if;
    end if;

  end process;

  p1_next_instruction_address <= A_EXT (A_WE_StdLogicVector((std_logic'((((do_branch OR do_jump) OR use_saved_next_address))) = '1'), ("0" & (target_address)), (("0" & (internal_next_instruction_address1)) + "0000000000001")), 12);
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      use_saved_next_address <= '0';
    elsif clk'event and clk = '1' then
      if std_logic'(pipe_run) = '1' then 
        if std_logic'((((do_jump OR do_branch)) AND NOT next_instruction_address_enable)) = '1' then 
          use_saved_next_address <= '1';
        elsif std_logic'(next_instruction_address_enable) = '1' then 
          use_saved_next_address <= '0';
        end if;
      end if;
    end if;

  end process;

  --vhdl renameroo for output signals
  d1_instruction_fifo_out <= internal_d1_instruction_fifo_out;
  --vhdl renameroo for output signals
  d1_instruction_fifo_read_data_bad <= internal_d1_instruction_fifo_read_data_bad;
  --vhdl renameroo for output signals
  force_trap_acknowledge <= internal_force_trap_acknowledge;
  --vhdl renameroo for output signals
  ic_read <= internal_ic_read2;
  --vhdl renameroo for output signals
  instruction_fifo_read_data_bad <= internal_instruction_fifo_read_data_bad;
  --vhdl renameroo for output signals
  next_instruction_address <= internal_next_instruction_address1;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity CPU_wait_counter is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal commit : IN STD_LOGIC;
                 signal d1_instruction_fifo_read_data_bad : IN STD_LOGIC;
                 signal do_force_trap : IN STD_LOGIC;