?? cpu.vhd
字號:
signal do_iSKPx : IN STD_LOGIC;
signal hold_for_hazard : IN STD_LOGIC;
signal is_cancelled : IN STD_LOGIC;
signal is_neutrino : IN STD_LOGIC;
signal must_run_to_completion : IN STD_LOGIC;
signal op_jmpcall : IN STD_LOGIC;
signal op_save_restore : IN STD_LOGIC;
signal pipe_run : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal subinstruction : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal trap_if_restore : IN STD_LOGIC;
signal trap_if_save : IN STD_LOGIC;
-- outputs:
signal feed_new_instruction : OUT STD_LOGIC
);
end entity CPU_wait_counter;
architecture europa of CPU_wait_counter is
signal instruction_delay : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal local_pipe_clk_en : STD_LOGIC;
signal pipe_state_we : STD_LOGIC;
signal unxshiftxxwait_counter_outputxwait_counter_shift_registerx2_in : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal unxshiftxxwait_counter_outputxwait_counter_shift_registerx2_out : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal wait_counter_output : STD_LOGIC;
signal wait_once_after : STD_LOGIC;
begin
local_pipe_clk_en <= commit;
pipe_state_we <= (local_pipe_clk_en AND NOT is_neutrino) AND NOT is_cancelled;
instruction_delay <= A_WE_StdLogicVector((std_logic'((((d1_instruction_fifo_read_data_bad) AND (commit)))) = '1'), "111", A_WE_StdLogicVector((std_logic'((wait_once_after)) = '1'), "110", A_WE_StdLogicVector((std_logic'((must_run_to_completion)) = '1'), "000", "111")));
wait_once_after <= (op_jmpcall) OR ((op_save_restore AND (((trap_if_save OR trap_if_restore) OR NOT is_neutrino))));
feed_new_instruction <= ((((wait_counter_output) OR (or_reduce(subinstruction)))) AND (NOT hold_for_hazard)) AND (NOT do_force_trap);
--wait_counter_shift_register_reg, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unxshiftxxwait_counter_outputxwait_counter_shift_registerx2_out <= "000";
elsif clk'event and clk = '1' then
if std_logic'(((pipe_run AND (NOT or_reduce(subinstruction))) AND NOT hold_for_hazard)) = '1' then
unxshiftxxwait_counter_outputxwait_counter_shift_registerx2_out <= unxshiftxxwait_counter_outputxwait_counter_shift_registerx2_in;
end if;
end if;
end process;
unxshiftxxwait_counter_outputxwait_counter_shift_registerx2_in <= A_WE_StdLogicVector((std_logic'((commit)) = '1'), instruction_delay, A_WE_StdLogicVector((true), Std_Logic_Vector'(A_ToStdLogicVector('1') & unxshiftxxwait_counter_outputxwait_counter_shift_registerx2_out(2 DOWNTO 1)), unxshiftxxwait_counter_outputxwait_counter_shift_registerx2_out));
wait_counter_output <= unxshiftxxwait_counter_outputxwait_counter_shift_registerx2_out(0);
end europa;
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity CPU_subinstruction_unit is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal commit : IN STD_LOGIC;
signal d1_instruction_fifo_out : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal d1_instruction_fifo_read_data_bad : IN STD_LOGIC;
signal feed_new_instruction : IN STD_LOGIC;
signal force_trap_acknowledge : IN STD_LOGIC;
signal is_cancelled : IN STD_LOGIC;
signal is_neutrino : IN STD_LOGIC;
signal pipe_run : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal is_subinstruction : OUT STD_LOGIC;
signal subinstruction : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
end entity CPU_subinstruction_unit;
architecture europa of CPU_subinstruction_unit is
signal internal_is_subinstruction1 : STD_LOGIC;
signal internal_subinstruction2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal local_pipe_clk_en : STD_LOGIC;
signal p1_subinstruction : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal p1_subinstruction_load_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal pipe_state_we : STD_LOGIC;
signal subcount_en : STD_LOGIC;
begin
local_pipe_clk_en <= commit;
pipe_state_we <= (local_pipe_clk_en AND NOT is_neutrino) AND NOT is_cancelled;
subcount_en <= feed_new_instruction AND pipe_run;
--subinstruction_counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
internal_subinstruction2 <= "00";
elsif clk'event and clk = '1' then
if std_logic'(subcount_en) = '1' then
internal_subinstruction2 <= p1_subinstruction;
end if;
end if;
end process;
p1_subinstruction <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_is_subinstruction1)) = '1'), (("0" & (internal_subinstruction2)) - "001"), ("0" & (p1_subinstruction_load_value))), 2);
p1_subinstruction_load_value <= A_WE_StdLogicVector((std_logic'((d1_instruction_fifo_read_data_bad)) = '1'), "00", A_WE_StdLogicVector((std_logic'((force_trap_acknowledge)) = '1'), "11", A_WE_StdLogicVector((std_logic'(((((((NOT d1_instruction_fifo_out(15) AND NOT d1_instruction_fifo_out(14)) AND NOT d1_instruction_fifo_out(13)) AND d1_instruction_fifo_out(12)) AND d1_instruction_fifo_out(11)) AND NOT d1_instruction_fifo_out(10)))) = '1'), "01", A_WE_StdLogicVector((std_logic'((((((((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14)) AND d1_instruction_fifo_out(13)) AND d1_instruction_fifo_out(12)) AND d1_instruction_fifo_out(11)) AND NOT d1_instruction_fifo_out(10))) AND NOT d1_instruction_fifo_out(9)) AND d1_instruction_fifo_out(8)))) = '1'), "11", A_WE_StdLogicVector((std_logic'(((((((NOT d1_instruction_fifo_out(15) AND NOT d1_instruction_fifo_out(14)) AND NOT d1_instruction_fifo_out(13)) AND d1_instruction_fifo_out(12)) AND d1_instruction_fifo_out(11)) AND d1_instruction_fifo_out(10)))) = '1'), "01", A_WE_StdLogicVector((std_logic'(((((((NOT d1_instruction_fifo_out(15) AND NOT d1_instruction_fifo_out(14)) AND d1_instruction_fifo_out(13)) AND NOT d1_instruction_fifo_out(12)) AND NOT d1_instruction_fifo_out(11)) AND NOT d1_instruction_fifo_out(10)))) = '1'), "01", A_WE_StdLogicVector((std_logic'(((((((NOT d1_instruction_fifo_out(15) AND NOT d1_instruction_fifo_out(14)) AND d1_instruction_fifo_out(13)) AND NOT d1_instruction_fifo_out(12)) AND NOT d1_instruction_fifo_out(11)) AND d1_instruction_fifo_out(10)))) = '1'), "01", A_WE_StdLogicVector((std_logic'(((((((NOT d1_instruction_fifo_out(15) AND NOT d1_instruction_fifo_out(14)) AND d1_instruction_fifo_out(13)) AND NOT d1_instruction_fifo_out(12)) AND d1_instruction_fifo_out(11)) AND NOT d1_instruction_fifo_out(10)))) = '1'), "01", A_WE_StdLogicVector((std_logic'(((((((NOT d1_instruction_fifo_out(15) AND NOT d1_instruction_fifo_out(14)) AND d1_instruction_fifo_out(13)) AND NOT d1_instruction_fifo_out(12)) AND d1_instruction_fifo_out(11)) AND d1_instruction_fifo_out(10)))) = '1'), "01", A_WE_StdLogicVector((std_logic'(((((((((((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14)) AND d1_instruction_fifo_out(13)) AND d1_instruction_fifo_out(12)) AND d1_instruction_fifo_out(11)) AND d1_instruction_fifo_out(10))) AND NOT d1_instruction_fifo_out(9)) AND NOT d1_instruction_fifo_out(8)) AND d1_instruction_fifo_out(7)) AND NOT d1_instruction_fifo_out(6)) AND d1_instruction_fifo_out(5)))) = '1'), "01", A_WE_StdLogicVector((std_logic'(((((((((((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14)) AND d1_instruction_fifo_out(13)) AND d1_instruction_fifo_out(12)) AND d1_instruction_fifo_out(11)) AND d1_instruction_fifo_out(10))) AND NOT d1_instruction_fifo_out(9)) AND NOT d1_instruction_fifo_out(8)) AND d1_instruction_fifo_out(7)) AND d1_instruction_fifo_out(6)) AND NOT d1_instruction_fifo_out(5)))) = '1'), "01", A_WE_StdLogicVector((std_logic'(((((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14)) AND NOT d1_instruction_fifo_out(13)) AND d1_instruction_fifo_out(12)) AND NOT d1_instruction_fifo_out(11)) AND NOT d1_instruction_fifo_out(10)))) = '1'), "01", A_WE_StdLogicVector((std_logic'(((((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14)) AND NOT d1_instruction_fifo_out(13)) AND d1_instruction_fifo_out(12)) AND NOT d1_instruction_fifo_out(11)) AND d1_instruction_fifo_out(10)))) = '1'), "01", A_WE_StdLogicVector((std_logic'(((((((((((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14)) AND d1_instruction_fifo_out(13)) AND d1_instruction_fifo_out(12)) AND d1_instruction_fifo_out(11)) AND d1_instruction_fifo_out(10))) AND d1_instruction_fifo_out(9)) AND NOT d1_instruction_fifo_out(8)) AND d1_instruction_fifo_out(7)) AND NOT d1_instruction_fifo_out(6)) AND NOT d1_instruction_fifo_out(5)))) = '1'), "01", A_WE_StdLogicVector((std_logic'(((((((((((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14)) AND d1_instruction_fifo_out(13)) AND d1_instruction_fifo_out(12)) AND d1_instruction_fifo_out(11)) AND d1_instruction_fifo_out(10))) AND d1_instruction_fifo_out(9)) AND NOT d1_instruction_fifo_out(8)) AND d1_instruction_fifo_out(7)) AND d1_instruction_fifo_out(6)) AND NOT d1_instruction_fifo_out(5)))) = '1'), "01", A_WE_StdLogicVector((std_logic'(((((((((((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14)) AND d1_instruction_fifo_out(13)) AND d1_instruction_fifo_out(12)) AND d1_instruction_fifo_out(11)) AND d1_instruction_fifo_out(10))) AND d1_instruction_fifo_out(9)) AND d1_instruction_fifo_out(8)) AND NOT d1_instruction_fifo_out(7)) AND d1_instruction_fifo_out(6)) AND NOT d1_instruction_fifo_out(5)))) = '1'), "01", "00"))))))))))))))));
internal_is_subinstruction1 <= (or_reduce((internal_subinstruction2))) AND (NOT is_neutrino);
--vhdl renameroo for output signals
is_subinstruction <= internal_is_subinstruction1;
--vhdl renameroo for output signals
subinstruction <= internal_subinstruction2;
end europa;
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity CPU_instruction_scheduler is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal d1_instruction_fifo_out : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal d1_instruction_fifo_read_data_bad : IN STD_LOGIC;
signal do_cancel_next_instruction : IN STD_LOGIC;
signal do_force_trap : IN STD_LOGIC;
signal do_iPFXx : IN STD_LOGIC;
signal do_iSKPx : IN STD_LOGIC;
signal do_skip : IN STD_LOGIC;
signal force_trap_acknowledge : IN STD_LOGIC;
signal hold_for_hazard : IN STD_LOGIC;
signal is_cancelled : IN STD_LOGIC;
signal must_run_to_completion : IN STD_LOGIC;
signal op_jmpcall : IN STD_LOGIC;
signal op_save_restore : IN STD_LOGIC;
signal pipe_run : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal trap_if_restore : IN STD_LOGIC;
signal trap_if_save : IN STD_LOGIC;
-- outputs:
signal commit : OUT STD_LOGIC;
signal feed_new_instruction : OUT STD_LOGIC;
signal is_cancelled_from_commit_stage : OUT STD_LOGIC;
signal is_neutrino : OUT STD_LOGIC;
signal is_subinstruction : OUT STD_LOGIC;
signal subinstruction : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
end entity CPU_instruction_scheduler;
architecture europa of CPU_instruction_scheduler is
component CPU_wait_counter is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal commit : IN STD_LOGIC;
signal d1_instruction_fifo_read_data_bad : IN STD_LOGIC;
signal do_force_trap : IN STD_LOGIC;
signal do_iSKPx : IN STD_LOGIC;
signal hold_for_hazard : IN STD_LOGIC;
signal is_cancelled : IN STD_LOGIC;
signal is_neutrino : IN STD_LOGIC;
signal must_run_to_completion : IN STD_LOGIC;
signal op_jmpcall : IN STD_LOGIC;
signal op_save_restore : IN STD_LOGIC;
signal pipe_run : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal subinstruction : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal trap_if_restore : IN STD_LOGIC;
signal trap_if_save : IN STD_LOGIC;
-- outputs:
signal feed_new_instruction : OUT STD_LOGIC
);
end component CPU_wait_counter;
component CPU_subinstruction_unit is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal commit : IN STD_LOGIC;
signal d1_instruction_fifo_out : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal d1_instruction_fifo_read_data_bad : IN STD_LOGIC;
signal feed_new_instruction : IN STD_LOGIC;
signal force_trap_acknowledge : IN STD_LOGIC;
signal is_cancelled : IN STD_LOGIC;
signal is_neutrino : IN STD_LOGIC;
signal pipe_run : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal is_subinstruction : OUT STD_LOGIC;
signal subinstruction : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
end component CPU_subinstruction_unit;
signal cancel_delay_slot_acknowledge : STD_LOGIC;
signal dont_forget_to_cancel_delay_slot : STD_LOGIC;
signal dont_forget_to_skip : STD_LOGIC;
signal instruction_not_ready : STD_LOGIC;
signal internal_commit1 : STD_LOGIC;
signal internal_feed_new_instruction : STD_LOGIC;
signal internal_is_neutrino1 : STD_LOGIC;
signal internal_is_subinstruction : STD_LOGIC;
signal internal_subinstruction1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal local_pipe_clk_en : STD_LOGIC;
signal p1_is_neutrino : STD_LOGIC;
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