/*******************************************************************************
 ****************************************************************************
 **                                                                             
 **                                                                             
 ** Project Name         : DDS                                            
 **                                                                             
 ** Author               : Daniel J. Morelli
 ** Creation Date        : 04/02/96 21:21:48                                              
 ** Version Number       : 1.0                                                 
 **                                                                             
 ** Revision History     :                                                      
 **                                                                             
 ** Date          Initials         Modification                                 
 **                                                                             
 **                                                                             
 ** Description          :                                                      
 **                                                                             
 ** This test bench test the phase accumulator
 ** 
 **                                                                             
 *******************************************************************************/
// Verilog Stimulus Data from SCS Waveform Editor v 2.8
// File: dds.tf - 3/11/96 10:56:32 PM

`timescale 1 ns / 1 ns

// Define Module for Test Fixture

module t;

// Create Dummy Wires to Connect to signals

reg RESETN, SYSCLK, PNCLK;
reg [31:0] FREQWORD;
reg FWWRN;
reg [7:0] PHASEWORD;
reg PWWRN;
wire [7:0] DACOUT;

integer fileptr;

// Instantiate the top Level Block

dds m( .RESETN(RESETN), .SYSCLK(SYSCLK), .FREQWORD(FREQWORD), 
       .FWWRN(FWWRN), .PHASEWORD(PHASEWORD), .PWWRN(PWWRN),
       .PNCLK(PNCLK), .DACOUT(DACOUT) );

// Code for all top level Inputs and BiDirs

  initial begin   // 'RESETN'
    RESETN = 1; #20;
    RESETN = 0; #30;
    RESETN = 1; #30;
  end  // RESETN

  initial begin   // 'PNCLK'
    forever
    begin  
      PNCLK = 1; #50;
      PNCLK = 0; #50;
    end
  end  // PNCLK

  initial begin   // 'SYSCLK'
    forever
    begin  // Patt_3
      SYSCLK = 1; #15;
      SYSCLK = 0; #15;
    end
  end  // SYSCLK

  initial begin   // 'FREQWORD'
    FREQWORD[31:0] = 32 'h 00000000; #80;
    FREQWORD[31:0] = 32 'h 01000000; #90;
  end  // FREQWORD

  initial begin   // 'FWWRN'
    FWWRN = 1; #110;
    FWWRN = 0; #30;
    FWWRN = 1; #30;
  end  // FWWRN

  initial begin   // 'PHASEWORD'
    PHASEWORD[7:0] = 8 'h 01; #170;
  end  // PHASEWORD

  initial begin   // 'PWWRN'
    PWWRN = 1; #200;
  end  // PWWRN

  initial 
  begin
		fileptr = $fopen("dds.out");
    	$fdisplay(fileptr,"TIME \t DACOUT \t");
		forever
		begin
			$fdisplay(fileptr,"%d",DACOUT);
			#30;
		end
	end

endmodule // t