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-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2004 Altera Corporation
-- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-- support information,  device programming or simulation file,  and any other
-- associated  documentation or information  provided by  Altera  or a partner
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-- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-- other  use  of such  megafunction  design,  netlist,  support  information,
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-- Generated by Quartus II Version 4.1 (Build Build 208 09/10/2004)
-- Created on Sun Oct 24 18:41:06 2004

-- read a number and display to 7segement display;
-- uses one-hot state machine;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY buffer_display IS
	PORT
	(
	   signal din10,din1: in std_logic_vector (3 downto 0);
	   signal done,RE,clk,reset: in std_logic;
	   signal dout10,dout1: out std_logic_vector (3 downto 0);
       signal start: out std_logic
	);
END buffer_display;

ARCHITECTURE buffer_display_architecture OF buffer_display IS
   constant s0: std_logic_vector (2 downto 0):="001";
   constant s1: std_logic_vector (2 downto 0):="010";
   constant s2: std_logic_vector (2 downto 0):="100";
   signal n_state,p_state: std_logic_vector (2 downto 0);
BEGIN
state:process(clk,reset)
begin
   if (reset='0') then  -- initial
        p_state<=s0;
   elsif (clk'event and clk='1') then
        p_state<=n_state;
   end if;
end process state;

comb:process(p_state,done,RE,din10,din1)
variable store1: std_logic_vector (3 downto 0);
variable store10: std_logic_vector (3 downto 0);
begin
    n_state<=p_state;
    if (p_state=s0) then -- initial state
       start<='0';
       dout10<="0000";
       dout1<="0000";
       if RE='0' then 
          n_state<=s1;
       else
          n_state<=s0;
       end if;
    end if;

    if (p_state=s1) then
       start<='0';
       if RE='0' then  -- read a number when RE# is 0
          n_state<=s1;
          store10:=din10;
          store1:=din1;
          dout10<=din10;
          dout1<=din1;
       elsif RE='1' then -- stop read when RE# become 1
          n_state<=s2;
       end if;
     end if;
     
     if (p_state=s2) then
        start<='1';      -- start the display_delay
        dout10<=store10;
        dout1<=store1;
        if done='0' then
              n_state<=s2;
        else
              n_state<=s0;
        end if;
       end if;
end process comb;
END buffer_display_architecture;