{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition " "Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 04 05:09:10 2004 " "Info: Processing started: Thu Nov 04 05:09:10 2004" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off buffer_display -c buffer_display " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off buffer_display -c buffer_display" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "buffer_display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file buffer_display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 buffer_display-buffer_display_architecture " "Info: Found design unit 1: buffer_display-buffer_display_architecture" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "buffer_display-buffer_display_architecture" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 45 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 buffer_display " "Info: Found entity 1: buffer_display" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "buffer_display" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 35 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "start buffer_display.vhd(60) " "Warning: VHDL Process Statement warning at buffer_display.vhd(60): signal or variable start may not be assigned a new value in every possible path through the Process Statement. Signal or variable start holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 60 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "dout10 buffer_display.vhd(60) " "Warning: VHDL Process Statement warning at buffer_display.vhd(60): signal or variable dout10 may not be assigned a new value in every possible path through the Process Statement. Signal or variable dout10 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 60 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "dout1 buffer_display.vhd(60) " "Warning: VHDL Process Statement warning at buffer_display.vhd(60): signal or variable dout1 may not be assigned a new value in every possible path through the Process Statement. Signal or variable dout1 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 60 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "store10 buffer_display.vhd(60) " "Warning: VHDL Process Statement warning at buffer_display.vhd(60): signal or variable store10 may not be assigned a new value in every possible path through the Process Statement. Signal or variable store10 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 60 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "store1 buffer_display.vhd(60) " "Warning: VHDL Process Statement warning at buffer_display.vhd(60): signal or variable store1 may not be assigned a new value in every possible path through the Process Statement. Signal or variable store1 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 60 0 0 } }  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "17 " "Info: Ignored 17 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "17 " "Info: Ignored 17 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "Netlist Optimizations " "Warning: Feature Netlist Optimizations is not available with your current license" {  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" "" "" { Text "D:/document/personal/inLiverpool/VHDL/project/assignment1/module/buffer_display/buffer_display.vhd" 53 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "56 " "Info: Implemented 56 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "35 " "Info: Implemented 35 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 04 05:09:12 2004 " "Info: Processing ended: Thu Nov 04 05:09:12 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}