-- debounce is used to eliminate the debounce of input signal
-- it is a ASM
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY debounce IS
PORT
	(
		signal SW : IN	STD_LOGIC;
		signal done : IN	STD_LOGIC;
		signal clk : IN	STD_LOGIC;
		signal reset: IN STD_LOGIC;
		signal START: OUT STD_LOGIC;
		signal SWdown : OUT STD_LOGIC
	);
end debounce;

ARCHITECTURE debounce_architecture OF debounce IS
	constant S0 :STD_LOGIC_VECTOR(1 downto 0):="00";  --declareation of states
	constant S1 :STD_LOGIC_VECTOR(1 downto 0):="01";
	constant S2 :STD_LOGIC_VECTOR(1 downto 0):="10";
	constant S3 :STD_LOGIC_VECTOR(1 downto 0):="11";
	signal p_state, n_state: STD_LOGIC_VECTOR(1 downto 0);
BEGIN
	state: PROCESS(clk,reset)
	BEGIN
		if(reset='0') then                  --set the initial state
			p_state<=S0;
		elsif(clk'EVENT AND clk='1') then
			p_state<=n_state;
		end if;
	end PROCESS state;
	
	comb: PROCESS(SW,done,p_state)
	BEGIN
		SWdown<='0';						
		START<='0';
		n_state<=p_state;
		if(p_state=S0) then		
			SWdown<='1';					
			START<='0';
			if(SW='1') then
				n_state<=S0;
			elsif(SW='0') then
				n_state<=S1;
			end if;
		end if;
		
		if(p_state=S1) then		
			SWdown<='1';			
			START<='1';		--start the counter.
			if(done='1') then
				n_state<=S2;
			elsif(done='0' and SW='1') then
				n_state<=S0;
			elsif(done='0' and SW='0') then
				n_state<=S1;
			end if;
		end if;

		if(p_state=S2) then				
			SWdown<='0';					
			START<='0';					
			if(SW='1') then
				n_state<=S3;
			elsif(SW='0') then
				n_state<=S2;
			end if;
		end if;
		
		if(p_state=S3) then				
			SWdown<='0';				
			START<='1';			--start the counter
			if(done='1') then
				n_state<=S0;
			elsif(done='0' and SW='1') then
				n_state<=S3;
			elsif(done='0' and SW='0') then
				n_state<=S2;
			end if;
		end if;
	end process comb;
end debounce_architecture;