entity sub_full_n is
generic(n:integer:=8);
port(x,y:in bit_vector(n-1 downto 0);
	 b_in:in bit;
	 b_out:out bit;
	 z:out bit_vector(n-1 downto 0));
end sub_full_n;

architecture sub_full_n of sub_full_n is

component sub_full
port(x,y,b_in:in bit;
	 b_out,z:out bit);
end component;

signal carry:bit_vector(n-2 downto 1);
begin
gen: for i in 0 to n-1 generate

first: if i=0 generate
u1:sub_full port map (x(i),y(i),b_in,carry(i),z(i));
end generate first;

second: if i=n-1 generate
u2: sub_full port map(x(i),y(i),carry(i-1),b_out,z(i));
end generate second;

third: if i>0 and i<n-1 generate
u3: sub_full port map (x(i),y(i),carry(i-1),carry(i),z(i));
end generate third;
end generate gen;

end sub_full_n;