?? traffic1.vhd
字號(hào):
library ieee;
use ieee.std_logic_1164.all;
entity traffic1 is
port(clk,rst,en:in std_logic;
R1,G1,Y1:out std_logic;
r2,g2,y2:out std_logic);
end ;
architecture light of traffic1 is
begin
process(clk,rst)
variable count1:integer range 0 to 31;
begin
if (en=1) then
cycle:for count1 in 0 to 31 loop
if rst='1' then R1<='0'; G1<='0'; Y1<='0';r2<='0';g2<='0';y2<='0';
end if;
case count1 is
when 0 to 14 =>G1<='1';Y1<='0';R1<='0';r2<='1';g2<='0';y2<='0';
when 15 to 17 =>G1<='0';Y1<='1';R1<='0';r2<='0';g2<='0';y2<='0';
when 18 to 20 =>R1<='1';Y1<='0';G1<='0';r2<='0';y2<='1';
when 21 to 30 =>y2<='0';g2<='1';
end case;
end for;
end if;
end ;
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