?? richic_vga_top.vhm
字號:
Q => Y_CNT_4_INT_5,
D => Y_CNT_6(4),
C => clk,
CLR => rst_n_i);
\II_y_cnt[5]\: FDC port map (
Q => Y_CNT_5_INT_6,
D => UN1_Y_CNT_1_S_5_N,
C => clk,
CLR => rst_n_i);
\II_y_cnt[6]\: FDC port map (
Q => Y_CNT_6_INT_7,
D => UN1_Y_CNT_1_S_6_N,
C => clk,
CLR => rst_n_i);
\II_y_cnt[7]\: FDC port map (
Q => Y_CNT_7_INT_8,
D => Y_CNT_6(7),
C => clk,
CLR => rst_n_i);
\II_y_cnt[8]\: FDC port map (
Q => Y_CNT_8_INT_9,
D => UN1_Y_CNT_1_S_8_N,
C => clk,
CLR => rst_n_i);
\II_y_cnt[9]\: FDC port map (
Q => Y_CNT_9_INT_10,
D => Y_CNT_6(9),
C => clk,
CLR => rst_n_i);
\II_x_cnt[0]\: FDC port map (
Q => X_CNT_0_INT_11,
D => X_CNT_6(0),
C => clk,
CLR => rst_n_i);
\II_x_cnt[1]\: FDC port map (
Q => X_CNT_1_INT_12,
D => UN6_X_CNT_S_1_N,
C => clk,
CLR => rst_n_i);
\II_x_cnt[2]\: FDC port map (
Q => X_CNT_2_INT_13,
D => UN6_X_CNT_S_2_N,
C => clk,
CLR => rst_n_i);
\II_x_cnt[3]\: FDC port map (
Q => X_CNT_3_INT_14,
D => X_CNT_6(3),
C => clk,
CLR => rst_n_i);
\II_x_cnt[4]\: FDC port map (
Q => X_CNT_4_INT_15,
D => UN6_X_CNT_S_4_N,
C => clk,
CLR => rst_n_i);
\II_x_cnt[5]\: FDC port map (
Q => X_CNT_5_INT_16,
D => X_CNT_6(5),
C => clk,
CLR => rst_n_i);
\II_x_cnt[6]\: FDC port map (
Q => X_CNT_6_INT_17,
D => X_CNT_6(6),
C => clk,
CLR => rst_n_i);
II_hsync: FDC port map (
Q => vga_hsync,
D => UN5_HSYNCLTO9_N,
C => clk,
CLR => rst_n_i);
II_vsync: FDC port map (
Q => vga_vsync,
D => UN5_VSYNCLTO9_N,
C => clk,
CLR => rst_n_i);
II_valid: FDC port map (
Q => valid,
D => VALID_3,
C => clk,
CLR => rst_n_i);
II_un5_validlto9: LUT4_L
generic map(
INIT => X"000B"
)
port map (
I0 => UN5_VALIDLTO6_N,
I1 => X_CNT_7_INT_18,
I2 => X_CNT_8_INT_19,
I3 => X_CNT_9_INT_20,
LO => UN5_VALIDLTO9_N);
II_valid_3_138: LUT4
generic map(
INIT => X"1055"
)
port map (
I0 => UN9_VALIDLTO9_N,
I1 => UN11_VALIDLTO6_N,
I2 => UN9_VALIDLTO9_1,
I3 => Y_CNT_9_INT_10,
O => VALID_3_138_N);
II_un5_validlto6: LUT4_L
generic map(
INIT => X"00BF"
)
port map (
I0 => UN5_VALIDLTO3_N,
I1 => X_CNT_4_INT_15,
I2 => X_CNT_5_INT_16,
I3 => X_CNT_6_INT_17,
LO => UN5_VALIDLTO6_N);
II_x_cnt14: LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => X_CNT14_3,
I1 => X_CNT14_4,
I2 => X_CNT_3_INT_14,
I3 => X_CNT_4_INT_15,
O => X_CNT14);
II_y_cnt14: LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => Y_CNT14_4,
I1 => Y_CNT14_5,
I2 => Y_CNT_6_INT_7,
I3 => Y_CNT_8_INT_9,
O => Y_CNT14);
II_un9_validlto9: LUT4_L
generic map(
INIT => X"0004"
)
port map (
I0 => UN9_VALIDLT9,
I1 => UN9_VALIDLTO9_1,
I2 => Y_CNT_6_INT_7,
I3 => Y_CNT_9_INT_10,
LO => UN9_VALIDLTO9_N);
II_un5_vsynclto9_4: LUT4_L
generic map(
INIT => X"0002"
)
port map (
I0 => UN5_VSYNCLTO9_3,
I1 => Y_CNT_3_INT_4,
I2 => Y_CNT_5_INT_6,
I3 => Y_CNT_9_INT_10,
LO => UN5_VSYNCLTO9_4);
II_un11_validlto6: LUT4
generic map(
INIT => X"AA80"
)
port map (
I0 => UN11_VALIDLTO6_2,
I1 => Y_CNT_0_INT_1,
I2 => Y_CNT_1_INT_2,
I3 => Y_CNT_2_INT_3,
O => UN11_VALIDLTO6_N);
II_un9_validlto5: LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => Y_CNT_2_INT_3,
I1 => Y_CNT_3_INT_4,
I2 => Y_CNT_4_INT_5,
I3 => Y_CNT_5_INT_6,
O => UN9_VALIDLT9);
II_un7_validlto5: LUT4
generic map(
INIT => X"001F"
)
port map (
I0 => X_CNT_2_INT_13,
I1 => X_CNT_3_INT_14,
I2 => X_CNT_4_INT_15,
I3 => X_CNT_5_INT_16,
O => UN7_VALIDLT9);
II_un5_validlto3: LUT3_L
generic map(
INIT => X"0B"
)
port map (
I0 => N_35_2_INT_21,
I1 => X_CNT_2_INT_13,
I2 => X_CNT_3_INT_14,
LO => UN5_VALIDLTO3_N);
II_un5_hsynclto9_1: LUT4_L
generic map(
INIT => X"0001"
)
port map (
I0 => X_CNT_6_INT_17,
I1 => X_CNT_7_INT_18,
I2 => X_CNT_8_INT_19,
I3 => X_CNT_9_INT_20,
LO => UN5_HSYNCLTO9_1);
II_un7_validlto9_1: LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => X_CNT_6_INT_17,
I1 => X_CNT_7_INT_18,
I2 => X_CNT_8_INT_19,
I3 => X_CNT_9_INT_20,
O => UN7_VALIDLTO9_1);
II_x_cnt14_4_0: LUT4_L
generic map(
INIT => X"4000"
)
port map (
I0 => X_CNT_1_INT_12,
I1 => X_CNT_6_INT_17,
I2 => X_CNT_7_INT_18,
I3 => X_CNT_8_INT_19,
LO => X_CNT14_4);
II_x_cnt14_3: LUT3
generic map(
INIT => X"40"
)
port map (
I0 => X_CNT_2_INT_13,
I1 => X_CNT_5_INT_16,
I2 => X_CNT_9_INT_20,
O => X_CNT14_3);
II_un5_vsynclto9_3: LUT4_L
generic map(
INIT => X"0001"
)
port map (
I0 => Y_CNT_4_INT_5,
I1 => Y_CNT_6_INT_7,
I2 => Y_CNT_7_INT_8,
I3 => Y_CNT_8_INT_9,
LO => UN5_VSYNCLTO9_3);
II_un11_validlto6_2: LUT4_L
generic map(
INIT => X"8000"
)
port map (
I0 => Y_CNT_3_INT_4,
I1 => Y_CNT_4_INT_5,
I2 => Y_CNT_5_INT_6,
I3 => Y_CNT_6_INT_7,
LO => UN11_VALIDLTO6_2);
II_y_cnt14_5: LUT4_L
generic map(
INIT => X"8000"
)
port map (
I0 => Y_CNT_0_INT_1,
I1 => Y_CNT_4_INT_5,
I2 => Y_CNT_7_INT_8,
I3 => Y_CNT_9_INT_10,
LO => Y_CNT14_5);
II_y_cnt14_4: LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => Y_CNT_1_INT_2,
I1 => Y_CNT_2_INT_3,
I2 => Y_CNT_3_INT_4,
I3 => Y_CNT_5_INT_6,
O => Y_CNT14_4);
II_un5_hsynclto3: LUT4
generic map(
INIT => X"0007"
)
port map (
I0 => X_CNT_0_INT_11,
I1 => X_CNT_1_INT_12,
I2 => X_CNT_2_INT_13,
I3 => X_CNT_3_INT_14,
O => UN5_HSYNCLTO3_N);
\II_y_cnt_i[0]\: LUT1
generic map(
INIT => X"1"
)
port map (
I0 => Y_CNT_0_INT_1,
O => y_cnt_i(0));
II_un11_validlto8_0: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => Y_CNT_7_INT_8,
I1 => Y_CNT_8_INT_9,
O => UN9_VALIDLTO9_1);
II_un1_y_cnt_1_axb_9: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => Y_CNT_9_INT_10,
O => UN1_Y_CNT_1_AXB_9);
II_un6_x_cnt_axb_9: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => X_CNT_9_INT_20,
O => UN6_X_CNT_AXB_9);
II_un5_validlto1: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => X_CNT_0_INT_11,
I1 => X_CNT_1_INT_12,
O => N_35_2_INT_21);
II_un1_y_cnt_1_s_9: XORCY port map (
LI => UN1_Y_CNT_1_AXB_9,
CI => UN1_Y_CNT_1_CRY_8,
O => UN1_Y_CNT_1_S_9_N);
II_un1_y_cnt_1_s_8: XORCY port map (
LI => UN1_Y_CNT_1_AXB_8,
CI => UN1_Y_CNT_1_CRY_7,
O => UN1_Y_CNT_1_S_8_N);
II_un1_y_cnt_1_cry_8: MUXCY_L port map (
DI => NN_1,
CI => UN1_Y_CNT_1_CRY_7,
S => UN1_Y_CNT_1_AXB_8,
LO => UN1_Y_CNT_1_CRY_8);
II_un1_y_cnt_1_s_7: XORCY port map (
LI => UN1_Y_CNT_1_AXB_7,
CI => UN1_Y_CNT_1_CRY_6,
O => UN1_Y_CNT_1_S_7_N);
II_un1_y_cnt_1_cry_7: MUXCY_L port map (
DI => NN_1,
CI => UN1_Y_CNT_1_CRY_6,
S => UN1_Y_CNT_1_AXB_7,
LO => UN1_Y_CNT_1_CRY_7);
II_un1_y_cnt_1_s_6: XORCY port map (
LI => UN1_Y_CNT_1_AXB_6,
CI => UN1_Y_CNT_1_CRY_5,
O => UN1_Y_CNT_1_S_6_N);
II_un1_y_cnt_1_cry_6: MUXCY_L port map (
DI => NN_1,
CI => UN1_Y_CNT_1_CRY_5,
S => UN1_Y_CNT_1_AXB_6,
LO => UN1_Y_CNT_1_CRY_6);
II_un1_y_cnt_1_s_5: XORCY port map (
LI => UN1_Y_CNT_1_AXB_5,
CI => UN1_Y_CNT_1_CRY_4,
O => UN1_Y_CNT_1_S_5_N);
II_un1_y_cnt_1_cry_5: MUXCY_L port map (
DI => NN_1,
CI => UN1_Y_CNT_1_CRY_4,
S => UN1_Y_CNT_1_AXB_5,
LO => UN1_Y_CNT_1_CRY_5);
II_un1_y_cnt_1_s_4: XORCY port map (
LI => UN1_Y_CNT_1_AXB_4,
CI => UN1_Y_CNT_1_CRY_3,
O => UN1_Y_CNT_1_S_4_N);
II_un1_y_cnt_1_cry_4: MUXCY_L port map (
DI => NN_1,
CI => UN1_Y_CNT_1_CRY_3,
S => UN1_Y_CNT_1_AXB_4,
LO => UN1_Y_CNT_1_CRY_4);
II_un1_y_cnt_1_s_3: XORCY port map (
LI => UN1_Y_CNT_1_AXB_3,
CI => UN1_Y_CNT_1_CRY_2,
O => UN1_Y_CNT_1_S_3_N);
II_un1_y_cnt_1_cry_3: MUXCY_L port map (
DI => NN_1,
CI => UN1_Y_CNT_1_CRY_2,
S => UN1_Y_CNT_1_AXB_3,
LO => UN1_Y_CNT_1_CRY_3);
II_un1_y_cnt_1_s_2: XORCY port map (
LI => UN1_Y_CNT_1_AXB_2,
CI => UN1_Y_CNT_1_CRY_1,
O => UN1_Y_CNT_1_S_2_N);
II_un1_y_cnt_1_cry_2: MUXCY_L port map (
DI => NN_1,
CI => UN1_Y_CNT_1_CRY_1,
S => UN1_Y_CNT_1_AXB_2,
LO => UN1_Y_CNT_1_CRY_2);
II_un1_y_cnt_1_s_1: XORCY port map (
LI => UN1_Y_CNT_1_AXB_1,
CI => UN1_Y_CNT_1_CRY_0,
O => UN1_Y_CNT_1_S_1_N);
II_un1_y_cnt_1_cry_1: MUXCY_L port map (
DI => NN_1,
CI => UN1_Y_CNT_1_CRY_0,
S => UN1_Y_CNT_1_AXB_1,
LO => UN1_Y_CNT_1_CRY_1);
II_un1_y_cnt_1_s_0: XORCY port map (
LI => UN1_Y_CNT_1_AXB_0,
CI => X_CNT14,
O => UN1_Y_CNT_1_S_0_N);
II_un1_y_cnt_1_cry_0: MUXCY_L port map (
DI => NN_1,
CI => X_CNT14,
S => UN1_Y_CNT_1_AXB_0,
LO => UN1_Y_CNT_1_CRY_0);
II_un6_x_cnt_s_9: XORCY port map (
LI => UN6_X_CNT_AXB_9,
CI => UN6_X_CNT_CRY_8,
O => UN6_X_CNT_S_9_N);
II_un6_x_cnt_s_8: XORCY port map (
LI => UN6_X_CNT_AXB_8,
CI => UN6_X_CNT_CRY_7,
O => UN6_X_CNT_S_8_N);
II_un6_x_cnt_cry_8: MUXCY_L port map (
DI => NN_1,
CI => UN6_X_CNT_CRY_7,
S => UN6_X_CNT_AXB_8,
LO => UN6_X_CNT_CRY_8);
II_un6_x_cnt_s_7: XORCY port map (
LI => UN6_X_CNT_AXB_7,
CI => UN6_X_CNT_CRY_6,
O => UN6_X_CNT_S_7_N);
II_un6_x_cnt_cry_7: MUXCY_L port map (
DI => NN_1,
CI => UN6_X_CNT_CRY_6,
S => UN6_X_CNT_AXB_7,
LO => UN6_X_CNT_CRY_7);
II_un6_x_cnt_s_6: XORCY port map (
LI => UN6_X_CNT_AXB_6,
CI => UN6_X_CNT_CRY_5,
O => UN6_X_CNT_S_6_N);
II_un6_x_cnt_cry_6: MUXCY_L port map (
DI => NN_1,
CI => UN6_X_CNT_CRY_5,
S => UN6_X_CNT_AXB_6,
LO => UN6_X_CNT_CRY_6);
II_un6_x_cnt_s_5: XORCY port map (
LI => UN6_X_CNT_AXB_5,
CI => UN6_X_CNT_CRY_4,
O => UN6_X_CNT_S_5_N);
II_un6_x_cnt_cry_5: MUXCY_L port map (
DI => NN_1,
CI => UN6_X_CNT_CRY_4,
S => UN6_X_CNT_AXB_5,
LO => UN6_X_CNT_CRY_5);
II_un6_x_cnt_s_4: XORCY port map (
LI => UN6_X_CNT_AXB_4,
CI => UN6_X_CNT_CRY_3,
O => UN6_X_CNT_S_4_N);
II_un6_x_cnt_cry_4: MUXCY_L port map (
DI => NN_1,
CI => UN6_X_CNT_CRY_3,
S => UN6_X_CNT_AXB_4,
LO => UN6_X_CNT_CRY_4);
II_un6_x_cnt_s_3: XORCY port map (
LI => UN6_X_CNT_AXB_3,
CI => UN6_X_CNT_CRY_2,
O => UN6_X_CNT_S_3_N);
II_un6_x_cnt_cry_3: MUXCY_L port map (
DI => NN_1,
CI => UN6_X_CNT_CRY_2,
S => UN6_X_CNT_AXB_3,
LO => UN6_X_CNT_CRY_3);
II_un6_x_cnt_s_2: XORCY port map (
LI => UN6_X_CNT_AXB_2,
CI => UN6_X_CNT_CRY_1,
O => UN6_X_CNT_S_2_N);
II_un6_x_cnt_cry_2: MUXCY_L port map (
DI => NN_1,
CI => UN6_X_CNT_CRY_1,
S => UN6_X_CNT_AXB_2,
LO => UN6_X_CNT_CRY_2);
II_un6_x_cnt_s_1: XORCY port map (
LI => UN6_X_CNT_AXB_1,
CI => UN6_X_CNT_CRY_0,
O => UN6_X_CNT_S_1_N);
II_un6_x_cnt_cry_1: MUXCY_L port map (
DI => NN_1,
CI => UN6_X_CNT_CRY_0,
S => UN6_X_CNT_AXB_1,
LO => UN6_X_CNT_CRY_1);
II_un6_x_cnt_cry_0: MUXCY_L port map (
DI => NN_1,
CI => NN_2,
S => UN6_X_CNT_AXB_0,
LO => UN6_X_CNT_CRY_0);
II_GND: GND port map (
G => NN_1);
II_VCC: VCC port map (
P => NN_2);
y_cnt(0) <= Y_CNT_0_INT_1;
y_cnt(1) <= Y_CNT_1_INT_2;
y_cnt(2) <= Y_CNT_2_INT_3;
y_cnt(3) <= Y_CNT_3_INT_4;
y_cnt(4) <= Y_CNT_4_INT_5;
y_cnt(5) <= Y_CNT_5_INT_6;
y_cnt(6) <= Y_CNT_6_INT_7;
y_cnt(7) <= Y_CNT_7_INT_8;
y_cnt(8) <= Y_CNT_8_INT_9;
y_cnt(9) <= Y_CNT_9_INT_10;
x_cnt(0) <= X_CNT_0_INT_11;
x_cnt(1) <= X_CNT_1_INT_12;
x_cnt(2) <= X_CNT_2_INT_13;
x_cnt(3) <= X_CNT_3_INT_14;
x_cnt(4) <= X_CNT_4_INT_15;
x_cnt(5) <= X_CNT_5_INT_16;
x_cnt(6) <= X_CNT_6_INT_17;
x_cnt(7) <= X_CNT_7_INT_18;
x_cnt(8) <= X_CNT_8_INT_19;
x_cnt(9) <= X_CNT_9_INT_20;
N_35_2 <= N_35_2_INT_21;
end beh;
-- No definition of black box work.ram1024x8.verilog
-- No definition of black box work.rom2048x8.verilog
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity richic_vga_top is
port(
clk : in std_logic;
rst_n : in std_logic;
line_num : in std_logic_vector (4 downto 0);
word_num : in std_logic_vector (4 downto 0);
ascii_in : in std_logic_vector (7 downto 0);
ascii_wea : in std_logic;
fg_color : in std_logic_vector (5 downto 0);
bg_color : in std_logic_vector (5 downto 0);
vga_hsync : out std_logic;
vga_vsync : out std_logic;
vga_red0 : out std_logic;
vga_red1 : out std_logic;
vga_green0 : out std_logic;
vga_green1 : out std_logic;
vga_blue0 : out std_logic;
vga_blue1 : out std_logic);
end richic_vga_top;
architecture beh of richic_vga_top is
signal Y_CNT : std_logic_vector (9 downto 0);
signal CLK_CNT : std_logic_vector (23 downto 0);
signal CLK_CNT_QXU : std_logic_vector (23 downto 0);
signal CLK_CNT_S : std_logic_vector (23 downto 0);
signal XPOS : std_logic_vector (9 downto 3);
signal XPOS_I : std_logic_vector (4 to 4);
signal YPOS : std_logic_vector (9 downto 1);
signal YPOS_I : std_logic_vector (2 to 2);
signal X_CNT : std_logic_vector (9 downto 0);
signal CHAR_SEL : std_logic_vector (9 downto 7);
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