LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY anti_tr2 IS
  PORT( clk:IN STD_LOGIC;
        key1,key2,key3:IN BIT;
         keyout1,keyout2,keyout3:OUT STD_LOGIC);
END anti_tr2;

ARCHITECTURE fengzhiqiu OF anti_tr2 IS
SIGNAL cp1:STD_LOGIC;
BEGIN
  PROCESS(clk)
  VARIABLE key:BIT;
  VARIABLE i:INTEGER RANGE 0 TO 40;
  variable sign:integer range 0 to 3;
  BEGIN
    key:=key1 or key2 or key3 OR '0';
    cp1<='0';
      IF (clk'EVENT AND clk='1') THEN
        IF (key1 or key2 or key3)='1' AND cp1='0' THEN
          if key1='1' then sign:=0;i:=i+1;
          elsif key2='1' then sign:=1;i:=i+1;
          elsif key3='1' then sign:=2;i:=i+1;
          end if;
        ELSE IF key='1' AND cp1='1' THEN
               i:=i;
             ELSE i:=0;
             END IF;
        END IF;
      END IF;

      IF i=40 THEN
        cp1<='1';
      END IF;
    case sign is
      when 1 => keyout1<=cp1;
      when 2 => keyout2<=cp1;
      when 3 => keyout3<=cp1;
      when others => keyout1<='0'; keyout2<='0'; keyout3<='0';
    end case;
  END PROCESS;
END fengzhiqiu;