//-------------------------------------------------   // Asynchronous reset    //-------------------------------------------------   always    begin      #50;       mr <= 1'b1 ;       #230;       mr <= 1'b0 ;       forever #100000;    end    always    begin : clk_stim      forever      begin         #(period / 2);          clk <= ~clk ;          if (test_done)         begin            clk <= ~clk ;            $display("TEST COMPLETE");            if (errors == 0)            begin               $display("There were no errors");            end            else            begin               $display("There were %d Errors", errors);            end            forever #100000;          end       end    end    always    begin : full_test      din <= 8'b00000000 ;       rd <= 1'b0 ;       wr <= 1'b0 ;       cs <= 1'b0 ;       ads <= 1'b0 ;       a <= 3'b000 ;       @(negedge mr);       wait_n_cycle(10);       //--------------------------------------------------------------------      // The first action is to write an initial value to every register      // outputs DTR, RTS, OUT1 and OUT2 will be checked      // also values of the registers will be checked      //--------------------------------------------------------------------      $display("\n    MPU writes initial registers\n");      // LINE Control register      cpu_write(initlcr0, lcradd, 1'b0);       // MODEM Control register      cpu_write(initmcr, mcradd, 1'b0);       $display("\n    Enable Interrupts\n");      @(posedge clk);       #cpu_tpd;       if (intr == 1'b0)      begin         $display ($stime,,"ns  INTR = 0  OK");      end      else      begin         $display ($stime,,"ns  INTR = 1  NOK");         errors <= errors + 1 ;       end       // IE register      cpu_write(initier, ieradd, 1'b0);       @(posedge clk);       #cpu_tpd;       if (intr == 1'b0)      begin         $display ($stime,,"ns  INTR = 0  OK");      end      else      begin         $display ($stime,,"ns  INTR = 1  NOK");         errors <= errors + 1 ;       end       $display("\n    Write to SCRATCH register");      cpu_write(initsr, sradd, 1'b0);       $display("\n    Write to FIFO CONTROL register");      cpu_write(initfcr0, fcradd, 1'b0);       $display("\n    Write to LINE CONTROL register");      cpu_write(({1'b1, initlcr0[6:0]}), lcradd, 1'b0);       $display("\n    Write to DIVISOR LSB register");      cpu_write(initdlr, dlradd, 1'b1);       $display("\n    Write to DIVISOR MSB register");      cpu_write(initdmr, dmradd, 1'b1);       wait_n_cycle(10);       $display("\n    MPU Reads initialized registers");      $display("\n    Write to LINE CONTROL register");      cpu_write(initlcr0, lcradd, 1'b0);       $display("\n    Read LINE CONTROL register");      cpu_read(lcradd, initlcr0, 1'b0, 1'b1);       $display("\n    Read MODEM CONTROL register");      cpu_read(mcradd, initmcr, 1'b0, 1'b1);       $display("\n    Read INTERRUPT ENABLE register");      cpu_read(ieradd, initier, 1'b0, 1'b1);       $display("\n    Read SCRATCH register");      cpu_read(sradd, initsr, 1'b0, 1'b1);       //---------------------------------------------      // Registers have been written and read once --      //---------------------------------------------      $display("\n    Write to LINE CONTROL register");      cpu_write(({1'b1, initlcr0[6:0]}), lcradd, 1'b0);       $display("\n    Read DIVISOR LSB register");      cpu_read(dlradd, initdlr, 1'b1, 1'b1);       $display("\n    Read DIVISOR MSB register");      cpu_read(dmradd, initdmr, 1'b1, 1'b1);       $display("\n    Read MODEM STATUS register");      cpu_read(msradd, 8'b00000000, 1'b0, 1'b1);       $display("\n    Read LINE STATUS register");      cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1);       $display("\n    Write LINE CONTROL register");      cpu_write(initlcr0, lcradd, 1'b0);       // RECEIVE BUFFER Register      cpu_read(rbradd, "UUUUUUUU", 1'b0, 1'b0);       $display("\n\n    Read INTERRUPT IDENTIFICATION register");      cpu_read(iiradd, 8'b11000001, 1'b0, 1'b1);       $display("\n    Read MODEM STATUS register");      cpu_read(msradd, 8'b00000000, 1'b0, 1'b1);       //-------------------------------------------------------------------------      //  8 bit messages + parity + 1 stop bit       //-------------------------------------------------------------------------      $display("\n    Write LINE CONTROL register");      cpu_write(initlcr0, lcradd, 1'b0);       cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1);       $display("\n    Write Transmitter holding register");      cpu_write(initthr0, thradd, 1'b0);       // LINE STATUS Register      cpu_read(lsradd, 8'b00000000, 1'b0, 1'b1);       wait_n_cycle(1690);       @(posedge clk);       #cpu_tpd;       if (intr == 1'b0)      begin         // Timeout hasn\'t reached         $display ($stime,,"ns  INTR = 0  OK");      end      else      begin         $display ($stime,,"ns  INTR = 1  NOK");         errors <= errors + 1 ;       end       wait_n_cycle(50);       @(posedge clk);       #cpu_tpd;       if (intr == 1'b1)      begin         // The timeout has reached         $display ($stime,,"ns  INTR = 1  OK");      end      else      begin         $display ($stime,,"ns  INTR = 0  NOK");         errors <= errors + 1 ;       end       //-----------------------------------------      //  7 bit messages 0 parity, 1 stop bit      //-----------------------------------------      // LINE Control register      cpu_write(initlcr1, lcradd, 1'b0);       // Transmitter Holding register      cpu_write(initthr2, thradd, 1'b0);       // RECEIVE BUFFER Register      cpu_read(rbradd, initthr0, 1'b0, 1'b1);       @(posedge clk);       #cpu_tpd;       if (intr == 1'b0)      begin         // Timeout has removed         $display ($stime,,"ns  INTR = 0  OK");      end      else      begin         $display ($stime,,"ns  INTR = 1  NOK");         errors <= errors + 1 ;       end       wait_n_cycle(1350);       @(posedge clk);       #cpu_tpd;       if (intr == 1'b0)      begin         // Timeout hasn\'t reached         $display ($stime,,"ns  INTR = 0  OK");      end      else      begin         $display ($stime,,"ns  INTR = 1  NOK");         errors <= errors + 1 ;       end       wait_n_cycle(50);       @(posedge clk);       #cpu_tpd;       if (intr == 1'b1)      begin         // The timeout has reached         $display ($stime,,"ns  INTR = 1  OK");      end      else      begin         $display ($stime,,"ns  INTR = 0  NOK");         errors <= errors + 1 ;       end       //7 bits - RECEIVE BUFFER Register      cpu_read(rbradd, (initthr2 & 8'b01111111), 1'b0, 1'b1);       @(posedge clk);       #cpu_tpd;       if (intr == 1'b0)      begin         // Timeout has removed         $display ($stime,,"ns  INTR = 0  OK");      end      else      begin         $display ($stime,,"ns  INTR = 1  NOK");         errors <= errors + 1 ;       end       //-----------------------------------------      //  6 bit messages + parity + 2 stop bits      //-----------------------------------------      // LINE Control register      cpu_write(initlcr2, lcradd, 1'b0);       // Transmitter Holding register      cpu_write(initthr1, thradd, 1'b0);       // LINE STATUS Register      cpu_read(lsradd, 8'b00000000, 1'b0, 1'b1);       wait_n_cycle(1500);       @(posedge clk);       #cpu_tpd;       if (intr == 1'b0)      begin         // Timeout hasn\'t reached         $display ($stime,,"ns  INTR = 0  OK");      end      else      begin         $display ($stime,,"ns  INTR = 1  NOK");         errors <= errors + 1 ;       end       wait_n_cycle(50);       @(posedge clk);       #cpu_tpd;       if (intr == 1'b1)      begin         // The timeout has reached         $display ($stime,,"ns  INTR = 1  OK");      end      else      begin         $display ($stime,,"ns  INTR = 0  NOK");         errors <= errors + 1 ;       end       // 6 bits - RECEIVE BUFFER Register      cpu_read(rbradd, (initthr1 & 8'b00111111), 1'b0, 1'b1);       @(posedge clk);       #cpu_tpd;       if (intr == 1'b0)      begin         // Timeout has removed         $display ($stime,,"ns  INTR = 0  OK");      end      else      begin         $display ($stime,,"ns  INTR = 1  NOK");         errors <= errors + 1 ;       end       //-----------------------------------------      //  5 bit messages      //-----------------------------------------      // LINE Control register      cpu_write(initlcr3, lcradd, 1'b0);       // Transmitter Holding register      cpu_write(initthr2, thradd, 1'b0);       wait_n_cycle(500);       // Transmitter Holding register      cpu_write(initthr1, thradd, 1'b0);       wait_n_cycle(1040);       @(posedge clk);       #cpu_tpd;       if (intr == 1'b0)      begin         // Timeout hasn\'t reached         $display ($stime,,"ns  INTR = 0  OK");      end      else      begin         $display ($stime,,"ns  INTR = 1  NOK");         errors <= errors + 1 ;       end       wait_n_cycle(50);       @(posedge clk);       #cpu_tpd;       if (intr == 1'b1)      begin         // The timeout has reached         $display ($stime,,"ns  INTR = 1  OK");      end      else      begin         $display ($stime,,"ns  INTR = 0  NOK");         errors <= errors + 1 ;       end       // 5 bits - RECEIVE BUFFER Register      cpu_read(rbradd, (initthr2 & 8'b00011111), 1'b0, 1'b1);       @(posedge clk);       #cpu_tpd;       if (intr == 1'b0)      begin         // Timeout has removed         $display ($stime,,"ns  INTR = 0  OK");      end      else      begin         $display ($stime,,"ns  INTR = 1  NOK");         errors <= errors + 1 ;       end       // 5 bits - RECEIVE BUFFER Register      cpu_read(rbradd, (initthr1 & 8'b00011111), 1'b0, 1'b1);       // Transmitter Holding register      cpu_write(initthr2, thradd, 1'b0);       wait_n_cycle(100);       // Transmitter Holding register      cpu_write(initthr0, thradd, 1'b0);       cpu_write(initthr1, thradd, 1'b0);       cpu_write(initthr1, thradd, 1'b0);       cpu_write(initthr0, thradd, 1'b0);       // FIFO Control register      cpu_write(initfcr1, fcradd, 1'b0);       wait_n_cycle(50);       // LINE STATUS Register      cpu_read(lsradd, 8'b00100000, 1'b0, 1'b1);       @(negedge rxrdyn);       wait_n_cycle(50);       // LINE STATUS Register      cpu_read(lsradd, 8'b01100001, 1'b0, 1'b1);       // RECEIVE BUFFER Register      cpu_read(rbradd, (initthr2 & 8'b00011111), 1'b0, 1'b1);       // LINE STATUS Register      cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1);       $display (" %d ERROR(S)", errors);      test_done <= 1'b1 ;       forever #100000;    endendmodule