?? h16550tb4.v
字號:
begin : xhdl_119 integer i; for(i = 0; i <= 20; i = i + 1) begin @(negedge baudout); end end // Modem status Register cpu_read(msradd, 8'b00000000, 1'b0, 1'b1); // LINE STATUS Register cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1); // LINE Control register cpu_write(initlcr, lcradd, 1'b0); //------------------------------------------------------------------------------------- // Next two messages will be written to Transmit holding register //------------------------------------------------------------------------------------- // THR register cpu_write((~initthr), thradd, 1'b0); //------------------------------------------------------------------------------------- // The next loop is done for polling THRE bit in Line status register // When it is \'1\' the Transmitter holding register is empty and next message data could be written //------------------------------------------------------------------------------------- begin : xhdl_120 integer i; for(i = 0; i <= 15; i = i + 1) begin @(negedge baudout); end end // THR register cpu_write((~initthr), thradd, 1'b0); //------------------------------------------------------------------------------------- // Check and wait interrupts // THRE bit activating //------------------------------------------------------------------------------------- @(posedge intr); $display("\n Checking DATA READY bit(DR) in Line Status Reg"); // LINE STATUS Register cpu_read(lsradd, 8'b00000001, 1'b0, 1'b1); // RECEIVE BUFFER Register cpu_read(rbradd, ~({(initthr[7] & initlcr[1] & initlcr[0]), (initthr[6] & initlcr[1]), (initthr[5] & (initlcr[1] | initlcr[0])), initthr[4:0]}), 1'b0, 1'b1); begin : xhdl_123 integer i; for(i = 0; i <= 120; i = i + 1) begin @(negedge baudout); end end //------------------------------------------------ // BREAK CONTROL bit(6) in LINE CONTROL REGISTER //------------------------------------------------ // LINE Control register cpu_write((initlcr[7:0] | 8'b01000000), lcradd, 1'b0); $display("\n Checking Transmitter Holding Reg(THRE) bit in Line Status Reg"); // LINE STATUS Register cpu_read(lsradd, 8'b00100000, 1'b0, 1'b1); // Interrupt identification Register cpu_read(iiradd, 8'b00000010, 1'b0, 1'b1); @(posedge intr); // Interrupt identification Register cpu_read(iiradd, 8'b00000110, 1'b0, 1'b1); begin : xhdl_126 integer i; //for(i = 0; i <= 200; i = i + 1) for(i = 0; i <= 180; i = i + 1) begin @(negedge baudout); end end // Disable Break cpu_write(initlcr, lcradd, 1'b0); begin : xhdl_1126 integer i; for(i = 0; i <= 50; i = i + 1) begin @(negedge baudout); end end // ALL Bits in Line Status Register have actived $display("\n Checking bits in Line Status Reg"); $display("\n Overrun error(OE), Parity error (PE), Framming error (FE) "); $display("\n Break Interrupt(BI) and Transmitter Empty (TEMT)"); // LINE STATUS Register cpu_read(lsradd, 8'b01111111, 1'b0, 1'b1); cpu_read(lsradd, 8'b01100001, 1'b0, 1'b1); //-------------------------------------------------------------------------- // INPUTS CTS, DSR, DCD and SIN and those effects to Modem Status Register and // interupts will be tested //-------------------------------------------------------------------------- $display("\n TESTING MODEM STATUS and INTERRUPT IDENTIFICATION REGISTERs when "); $display("\n Clear To Send(CTS), Data Set Ready(DSR), "); $display("\n Ring Indicator(RI) and Data Carrier detect(DCD) inputs"); cts <= 1'b0 ; dsr <= 1'b0 ; dcd <= 1'b0 ; ri <= 1'b0 ; // Interrupt identification Register cpu_read(iiradd, 8'b00000100, 1'b0, 1'b1); // LINE STATUS Register cpu_read(lsradd, 8'b01100001, 1'b0, 1'b1); // RECEIVE BUFFER Register cpu_read(rbradd, 8'b00000000, 1'b0, 1'b1); // MODEM STATUS Register cpu_read(msradd, 8'b11111011, 1'b0, 1'b1); @(posedge clk); #cpu_tpd; if (intr == 1'b1) begin $display($stime,,"ns INTR NOK"); errors <= errors + 1 ; end begin : xhdl_138 integer i; for(i = 0; i <= 2; i = i + 1) begin @(negedge baudout); end end cts <= 1'b1 ; @(negedge baudout); @(posedge clk); #cpu_tpd; if (intr == 1'b0) begin $display($stime,,"ns INTR NOK"); errors <= errors + 1 ; end // Interrupt identification Register cpu_read(iiradd, 8'b00000000, 1'b0, 1'b1); // MODEM STATUS Register cpu_read(msradd, 8'b11100001, 1'b0, 1'b1); begin : xhdl_141 integer i; for(i = 0; i <= 2; i = i + 1) begin @(negedge baudout); end end dsr <= 1'b1 ; @(negedge baudout); @(posedge clk); #cpu_tpd; if (intr == 1'b0) begin $display($stime,,"ns INTR NOK"); errors <= errors + 1 ; end // Interrupt identification Register cpu_read(iiradd, 8'b00000000, 1'b0, 1'b1); // MODEM STATUS Register cpu_read(msradd, 8'b11000010, 1'b0, 1'b1); begin : xhdl_144 integer i; for(i = 0; i <= 2; i = i + 1) begin @(negedge baudout); end end dcd <= 1'b1 ; @(negedge baudout); @(posedge clk); #cpu_tpd; if (intr == 1'b0) begin $display($stime,,"ns INTR NOK"); errors <= errors + 1 ; end // Interrupt identification Register cpu_read(iiradd, 8'b00000000, 1'b0, 1'b1); // MODEM STATUS Register cpu_read(msradd, 8'b01001000, 1'b0, 1'b1); begin : xhdl_147 integer i; for(i = 0; i <= 2; i = i + 1) begin @(negedge baudout); end end ri <= 1'b1 ; @(negedge baudout); @(posedge clk); #cpu_tpd; if (intr == 1'b0) begin $display($stime,,"ns INTR NOK"); errors <= errors + 1 ; end // Interrupt identification Register cpu_read(iiradd, 8'b00000000, 1'b0, 1'b1); // MODEM STATUS Register cpu_read(msradd, 8'b00000100, 1'b0, 1'b1); begin : xhdl_150 integer i; for(i = 0; i <= 2; i = i + 1) begin @(negedge baudout); end end cts <= 1'b0 ; @(negedge baudout); @(posedge clk); #cpu_tpd; if (intr == 1'b0) begin $display($stime,,"ns INTR NOK"); errors <= errors + 1 ; end // Interrupt identification Register cpu_read(iiradd, 8'b00000000, 1'b0, 1'b1); // MODEM STATUS Register cpu_read(msradd, 8'b00010001, 1'b0, 1'b1); begin : xhdl_153 integer i; for(i = 0; i <= 2; i = i + 1) begin @(negedge baudout); end end dsr <= 1'b0 ; @(negedge baudout); @(posedge clk); #cpu_tpd; if (intr == 1'b0) begin $display($stime,,"ns INTR NOK"); errors <= errors + 1 ; end // Interrupt identification Register cpu_read(iiradd, 8'b00000000, 1'b0, 1'b1); // MODEM STATUS Register cpu_read(msradd, 8'b00110010, 1'b0, 1'b1); begin : xhdl_156 integer i; for(i = 0; i <= 2; i = i + 1) begin @(negedge baudout); end end dcd <= 1'b0 ; @(negedge baudout); @(posedge clk); #cpu_tpd; if (intr == 1'b0) begin $display($stime,,"ns INTR NOK"); errors <= errors + 1 ; end // Interrupt identification Register cpu_read(iiradd, 8'b00000000, 1'b0, 1'b1); // MODEM STATUS Register cpu_read(msradd, 8'b10111000, 1'b0, 1'b1); begin : xhdl_159 integer i; for(i = 0; i <= 2; i = i + 1) begin @(negedge baudout); end end ri <= 1'b0 ; //----------------------------------------------------------------------------------- // Interrupt should NOT be activated because when there is falling edge in RI signal // the interrupt will not be generated //----------------------------------------------------------------------------------- @(posedge clk); #cpu_tpd; if (intr == 1'b1) begin $display($stime,,"ns INTR NOK"); errors <= errors + 1 ; end //@(posedge intr); // Interrupt identification Register //cpu_read(iiradd, 8'b00000110, 1'b0, 1'b1); cpu_read(iiradd, 8'b00000001, 1'b0, 1'b1); // MODEM STATUS Register cpu_read(msradd, 8'b11110000, 1'b0, 1'b1); //----------------------- // LOOP MODE TEST //----------------------- begin : xhdl_162 integer i; for(i = 0; i <= 150; i = i + 1) begin @(negedge baudout); end end $display($stime,,"ns TESTING LOOP MODE"); // LINE Control register cpu_write(initlcr, lcradd, 1'b0); // MODEM Control register cpu_write((initmcr | 8'b00010000), mcradd, 1'b0); $display("\n Check outputs : DTR, RTS, OUT1 and OUT2 "); @(posedge clk); #cpu_tpd; if (dtr == 1'b1) begin $display($stime,,"ns DTR output OK"); end else begin $display($stime,,"ns DTR output NOK"); errors <= errors + 1 ; end if (rts == 1'b1) begin $display($stime,,"ns RTS output OK"); end else begin $display($stime,,"ns RTS output NOK"); errors <= errors + 1 ; end if (out1 == 1'b1) begin $display($stime,,"ns OUT1 output OK"); end else begin $display($stime,,"ns OUT1 output NOK"); errors <= errors + 1 ; end if (out2 == 1'b1) begin $display($stime,,"ns OUT2 output OK"); end else begin $display($stime,,"ns OUT2 output NOK"); errors <= errors + 1 ; end // MODEM STATUS Register cpu_read(msradd, 8'b01101001, 1'b0, 1'b1); // LINE STATUS Register //cpu_read(lsradd, 8'b01111000, 1'b0, 1'b1); cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1); // Transmitter Holding register cpu_write(8'b10001110, thradd, 1'b0); // RECEIVE BUFFER Register cpu_read(rbradd, 8'b00000000, 1'b0, 1'b1); begin : xhdl_176 integer i; for(i = 0; i <= 9; i = i + 1) begin @(negedge baudout); end end // Interrupt identification Register //cpu_read(iiradd, 8'b00000110, 1'b0, 1'b1); cpu_read(iiradd, 8'b00000010, 1'b0, 1'b1); // since the INTR will go high when it start transmit, the rbreg data won\'t // be threg data when INTR is high begin : xhdl_177 integer i; for(i = 0; i <= 200; i = i + 1) begin @(negedge baudout); end end // RECEIVE BUFFER Register cpu_read(rbradd, 8'b10001110, 1'b0, 1'b1); do_reset <= 1'b1 ; wait_n_cycle(5); $display("\n MPU READs registers after RESET"); $display("\n Read LINE CONTROL register after RESET"); cpu_read(lcradd, 8'b00000000, 1'b0, 1'b1); $display("\n Read MODEM CONTROL register after RESET"); cpu_read(mcradd, 8'b00000000, 1'b0, 1'b1); $display("\n Read INTERRUPT ENABLE register after RESET"); cpu_read(ieradd, 8'b00000000, 1'b0, 1'b1); $display("\n Read SCRATCH register after RESET"); cpu_read(sradd, 8'b00000000, 1'b0, 1'b1); $display("\n Write to LINE CONTROL register"); cpu_write(({1'b1, initlcr[6:0]}), lcradd, 1'b0); $display("\n READ DIVISOR LSB register after RESET"); cpu_read(dlradd, 8'b00000001, 1'b1, 1'b1); $display("\n READ DIVISOR MSB register after RESET"); cpu_read(dmradd, initdmr, 1'b1, 1'b1); $display("\n Read MODEM STATUS register after RESET"); cpu_read(msradd, ({~dcd, ~ri, ~dsr, ~cts, 4'b0000}), 1'b0, 1'b1); $display("\n Read LINE STATUS register after RESET"); cpu_read(lsradd, 8'b01100000, 1'b0, 1'b1); $display("\n Read INTERRUPT IDENTIFICATION register after RESET"); cpu_read(iiradd, 8'b00000001, 1'b0, 1'b1); $display (" %d ERROR(S)", errors); test_done <= 1'b1 ; forever #100000; endendmodule?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -