//////////////////////////////////////////////////////////////////////////////////////////////////----------------------------------------------------------------------//// Copyright (c) 2002-2003 CAST, inc.//// Please review the terms of the license agreement before using this// file.  If you are not an authorized user, please destroy this source// code file and notify CAST immediately that you inadvertently received// an unauthorized copy.//----------------------------------------------------------------------////  Project       : H16550 UART////  File          : h16550tb6.vhd////  Dependencies  : h16550w.vhd////  Model Type    : Simulation Model (Testbench)////  Description   : H16550 testbench 6////  Designer      : JV////  QA Engineer   : Joram Heilbronner////  Creation Date : 13-January-2002////  Last Update   : 15-February-2002////  Version       : 2.0V////  History       : 1.1 - 02/18/02    VHDL Release////  Tested Operations:  RECEIVING LINE STATUS (OE, PE, FE, BI)//                      INTERRUPTS REGISTERS; IDETIFICATION & ENABLE////----------------------------------------------------------------------`timescale 1 ns/1 psmodule h16550tb ();   parameter scale  = 1.0;   integer index;    reg enable_sin;    integer errors;    reg done;    reg mr;    reg[2:0] a;    reg ads;    reg cs;    reg wr;    reg rd;    reg clk;    reg rclk;    reg sin;    reg cts;    reg dsr;    reg dcd;    reg ri;    wire ddis;    wire baudout;    wire sout;    wire rxrdyn;    wire txrdyn;    wire rts;    wire dtr;    wire out1;    wire out2;    wire intr;    wire[7:0] dout;    wire[7:0] data;    reg[7:0] din;    parameter period = 100 * scale;    parameter cpu_tpd = period / 3;    parameter cpu_trdwr = cpu_tpd / 2;    reg debug;    parameter[7:0] initlcr = 8'b00011000;    parameter[7:0] initmcr = 8'b00000101;    parameter[7:0] initier = 8'b00000001;    parameter[7:0] initsr = 8'b11011111;    parameter[7:0] initdlr = 8'b00000001;    parameter[7:0] initdmr = 8'b00000000;    parameter[7:0] initthr = 8'b01010110;    parameter[2:0] rbradd = 3'b000;    parameter[2:0] thradd = 3'b000;    parameter[2:0] dlradd = 3'b000;    parameter[2:0] dmradd = 3'b001;    parameter[2:0] ieradd = 3'b001;    parameter[2:0] iiradd = 3'b010;    parameter[2:0] lcradd = 3'b011;    parameter[2:0] mcradd = 3'b100;    parameter[2:0] lsradd = 3'b101;    parameter[2:0] msradd = 3'b110;    parameter[2:0] sradd = 3'b111;    // Testbench frame data to receiver block   reg[7:0] sin_data;    reg[7:0] sin_data2;    reg[7:0] sin_data_pe;    reg[7:0] sin_data_fe;    reg[7:0] sin_data_oe;    reg gnd;    reg vcc;    task wait_n_cycle;      input ncycle;      integer ncycle;      begin         begin : xhdl_8            integer i;            for(i = ncycle; i >= 0; i = i - 1)            begin               @(posedge clk);            end         end      end   endtask   task cpu_write;      input[7:0] data;      input[2:0] reg_addr;      input dlab;      begin         @(posedge clk);         #cpu_tpd;         a <= reg_addr ;         cs <= 1'b1 ;         din <= data ;         #cpu_trdwr;         wr <= 1'b1 ;         @(posedge clk);         #cpu_tpd;         wr <= 1'b0 ;         #cpu_trdwr;         cs <= 1'b0 ;         din <= 8'bZZZZZZZZ ;         $write($stime,,"ns MPU Write: Register");         case (reg_addr)            3'b000 :                     begin                        if (dlab)                        begin                           $write(" DLR");                        end                        else                        begin                           $write(" THR");                        end                     end            3'b001 :                     begin                        if (dlab)                        begin                           $write(" DMR");                        end                        else                        begin                           $write(" IER");                        end                     end            3'b010 :                     begin                        $write(" FCR ");                     end            3'b011 :                     begin                        $write(" LCR ");                     end            3'b100 :                     begin                        $write(" MCR ");                     end            3'b101 :                     begin                        $write(" LSR ");                     end            3'b110 :                     begin                        $write(" MSR ");                     end            3'b111 :                     begin                        $write(" SCR ");                     end            default :                     begin                        $write(" Unknown ");                     end         endcase         $display("= %b", data);      end   endtask   task cpu_read;      input[2:0] reg_addr;      input[7:0] ref;      input dlab;      input check;      begin         @(posedge clk);         #cpu_tpd;         a <= reg_addr ;         cs <= 1'b1 ;         #cpu_trdwr;         rd <= 1'b1 ;         @(posedge clk);         #cpu_tpd;         rd <= 1'b0 ;         $write($stime,,"ns  MPU Read: Register");         case (reg_addr)            3'b000 :                     begin                        if (dlab)                        begin                           $write(" DLR");                        end                        else                        begin                           $write(" RBR");                        end                     end            3'b001 :                     begin                        if (dlab)                        begin                           $write(" DMR");                        end                        else                        begin                           $write(" IER");                        end                     end            3'b010 :                     begin                        $write(" ISR ");                     end            3'b011 :                     begin                        $write(" LCR ");                     end            3'b100 :                     begin                        $write(" MCR ");                     end            3'b101 :                     begin                        $write(" LSR ");                     end            3'b110 :                     begin                        $write(" MSR ");                     end            3'b111 :                     begin                        $write(" SCR ");                     end            default :                     begin                        $write(" Unknown ");                     end         endcase         if (check)         begin            $write("= %b", dout);         end         else          begin            $display("= %b", dout);         end         if (check)         begin            if (dout != ref)            begin               $write(" ##### NOK");               $write(" EXPECTED RESULT IS  ");               $display(" %b  #####", ref);               errors <= errors + 1 ;            end            else            begin               $display("  OK");            end         end         #cpu_trdwr;         cs <= 1'b0 ;         @(posedge clk);         #cpu_tpd;      end   endtask   initial   begin      index <= 0;      enable_sin <= 1'b0;      errors <= 0;      done <= 1'b0;      mr <= 1'b1;      a <= 3'b000 ;      ads <= 1'b1;      cs <= 1'b0;      wr <= 1'b0;      rd <= 1'b0;      clk <= 1'b0;      rclk <= 1'b0;      sin <= 1'b1;      cts <= 1'b1;      dsr <= 1'b1;      dcd <= 1'b1;      ri <= 1'b1;      din <= 8'b00000000 ;      debug <= 1'b0;      sin_data <= 8'b11000110;      sin_data2 <= 8'b11011100;      sin_data_pe <= 8'b11001010;      sin_data_fe <= 8'b01001110;      sin_data_oe <= 8'b11011100;      gnd <= 1'b0;      vcc <= 1'b1;   end   h16550w u1 (.a(a), .adsn(ads), .cs0(cs), .cs1(vcc), .cs2n(gnd), .wr(wr),   .rd(rd), .mr(mr), .clk(clk), .rclk(rclk), .sin(sin), .ctsn(cts), .dsrn(dsr), .dcdn(dcd),   .rin(ri), .ddis(ddis), .baudoutn(baudout), .sout(sout), .rtsn(rts), .dtrn(dtr),   .out1n(out1), .out2n(out2), .intr(intr), .rxrdyn(rxrdyn), .txrdyn(txrdyn),   .dout(dout[7:0]), .din(din[7:0]));    //-------------------------------------------------      // Infinite clock generator   //-------------------------------------------------   always @(baudout)   begin       rclk <= baudout ;   end   //-------------------------------------------------   // Asynchronous reset    //-------------------------------------------------   always    begin      #50;       mr <= 1'b1 ;       #230;       mr <= 1'b0 ;       forever #100000;    end    always    begin : clk_stim      forever      begin         #(period / 2);          clk <= ~clk ;          if (done)         begin            clk <= ~clk ;            $display("TEST COMPLETE");            if (errors == 0)            begin               $display("There were no errors");            end            else            begin               $display("There were %d Errors", errors);            end              forever #100000;          end       end    end    //------------------------------------------------------------   // This process generates data to SIN input.   // SIN_DATA vector consists all frame bits    //    // Main process activates this process by ENABLE_SIN signal   //------------------------------------------------------------   always    begin : xhdl_36      index <= 0 ;       @(posedge enable_sin);       wait_n_cycle(10);       $display($stime,,"ns :   Writing datastream SIN_DATA_PE (11001010)");       begin : xhdl_11         integer sd0;         for(sd0 = 0; sd0 <= 7; sd0 = sd0 + 1)         begin            sin <= sin_data_pe[index] ;             index <= index + 1 ;             begin : xhdl_12               integer bo0;               for(bo0 = 0; bo0 <= 15; bo0 = bo0 + 1)               begin                  @(negedge baudout);                end            end          end      end       index <= 0 ;       @(posedge enable_sin);       wait_n_cycle(10);       $display($stime,,"ns :   Writing datastream SIN_DATA_FE (01001110)");       begin : xhdl_15         integer sd1;         for(sd1 = 0; sd1 <= 7; sd1 = sd1 + 1)         begin            sin <= sin_data_fe[index] ;             index <= index + 1 ;             begin : xhdl_16               integer bo1;               for(bo1 = 0; bo1 <= 15; bo1 = bo1 + 1)               begin                  @(negedge baudout);                end            end          end      end       begin : xhdl_18         integer bo2;         for(bo2 = 0; bo2 <= 114; bo2 = bo2 + 1)         begin            @(negedge baudout);          end      end       index <= 0 ;       wait_n_cycle(10);       // Disable the break - set sin = '1'      sin <= 1'b1;      wait_n_cycle(8);      sin <= 1'b0;      wait_n_cycle(20);      $display($stime,,"ns :   Writing datastream SIN_DATA_OE (11011100)");       begin : xhdl_21         integer sd2;         for(sd2 = 0; sd2 <= 7; sd2 = sd2 + 1)         begin            sin <= sin_data_oe[index] ;             index <= index + 1 ;             begin : xhdl_22               integer bo3;               for(bo3 = 0; bo3 <= 15; bo3 = bo3 + 1)               begin                  @(negedge baudout);                end            end          end      end       @(posedge enable_sin);       index <= 0 ;       wait_n_cycle(10);       $display($stime,,"ns :   Writing datastream SIN_DATA (11000110)");       begin : xhdl_25         integer sd3;         for(sd3 = 0; sd3 <= 7; sd3 = sd3 + 1)         begin            sin <= sin_data[index] ;             index <= index + 1 ;             begin : xhdl_26               integer bo4;               for(bo4 = 0; bo4 <= 15; bo4 = bo4 + 1)               begin