//////////////////////////////////////////////////////////////////////////////////////////////////----------------------------------------------------------------------//// Copyright (c) 2002-2003 CAST, inc.//// Please review the terms of the license agreement before using this// file.  If you are not an authorized user, please destroy this source// code file and notify CAST immediately that you inadvertently received// an unauthorized copy.//----------------------------------------------------------------------////  Project       : H16550 UART////  File          : h16550.v////  Dependencies  : rwcontrol.v, uart_reg.v, intcontrol.v, baudgen.v,//                  rxblock.v, txblock.v, fifoctrl.v, uart_fifo.v////  Model Type    : Synthesizable Core////  Description   : h16550 UART with FIFO// //  Designer      : JU////  QA Engineer   : JH////  Creation Date : 02-January-2002////  Last Update   : 20-June-2003////  Version       : 2.0V////  History       : 1.1 - 02/18/02    VHDL Release//                  1.2 - 04/16/02    Reduce Receiver's RAMs//                                    Reduce Receiver and Transmitter read/write//                                    address to 4 bits//                                    Performance (size) improved//                                    Transmit Fifo reset will reset read/write pointer to 0//                                    Receiver Fifo reset will reset read/write pointer to 0//                  2.0 - 06/20/03    Add prevrdlsr to uart_reg block//                                    Rename RXRDY and TXRDY to RXRDYN and TXRDYN//                                    Add thrint5 in uart_reg and intcontrol//                                    Add txfifo_2char in fifoctrl and txblock////----------------------------------------------------------------------`timescale 1 ns/1 psmodule h16550 (mr, clk, rclk, cs, rd, wr, ctsn, dcdn, dsrn, rin, sin, a, din, ddis, sout, baudoutn, dtrn, rtsn, out1n, out2n, intr, rxrdyn, txrdyn, dout);   `include "h16550_params.v"   input mr; // Master Reset   input clk; // System Clock   input rclk; // Receiver Clock   input cs; // Latched Chip Enable   input rd; // Read Enable   input wr; // Write Enable   input ctsn; // Clear To Send Enable   input dcdn; // Data Carrier Detect   input dsrn; // Data Set Ready   input rin; // Ring indicator   input sin; // Serial Input   input[ADDR_WIDTH - 1:0] a; // Latched address   input[DATA_WIDTH - 1:0] din; // Data input bus   output ddis; // Data Bus driver disable   wire ddis;   output sout; // Serial ouput   wire sout;   output baudoutn; // Baud out   wire baudoutn;   output dtrn; // Data terminal ready   wire dtrn;   output rtsn; // Request To send   wire rtsn;   output out1n; // Output 1   wire out1n;   output out2n; // Output 2   wire out2n;   output intr; // Interrupt   wire intr;   output rxrdyn; // Receiver ready   wire rxrdyn;   output txrdyn; // Transmitter ready   wire txrdyn;   output[DATA_WIDTH - 1:0] dout;    wire[DATA_WIDTH - 1:0] dout;   //------------------------   // component declarations   //------------------------   wire[DATA_WIDTH - 1:0] rbreg;    wire[DATA_WIDTH - 1:0] dmreg;    wire[DATA_WIDTH - 1:0] dlreg;    wire[DATA_WIDTH - 1:0] lcreg;    wire[5:0] fcreg;    wire[4:0] mcreg;    wire[3:0] iereg;    wire[3:0] iireg;    wire[DATA_WIDTH - 1:0] msreg;    wire[DATA_WIDTH - 1:0] sreg;    wire[DATA_WIDTH - 1:0] lsreg;    wire[DATA_WIDTH - 1:0] threg;    wire[10:0] rxf;    wire lsreg_b0;    wire lsreg_b3;    wire lsreg_b4;    wire lsreg11;    wire lsreg_b2;    wire rbrint;    wire rbrint1;    wire thrint;    wire thrint1;    wire thrint4;    wire thrint5;    wire ena_ier;    wire ena_lcr;    wire ena_mcr;    wire ena_sr;    wire write_rxfifo;    wire read_txfifo;    wire read_msr;    wire read_iir;    wire write_thr;    wire read_lsr;    wire txbaud;    wire sin_org;    wire sout_org;    wire write_dlr;    wire write_dmr;    wire temt;    wire at_trig_level;    wire rxfifo_full;    wire txfifo_empty;    wire rxfifo_empty;    wire fcreg11;    wire fcreg21;    wire lsreg51;    wire lsreg_b7;    wire toint1;    wire toint;    wire topre;    wire topre2;    wire prevrdlsr;    wire txfifo_2char;    rwcontrol u_rwcontrol (.a(a), .cs(cs), .rd(rd), .mr(mr), .clk(clk), .fcreg0(fcreg[0]), .rbreg(rbreg), .dmreg(dmreg), .dlreg(dlreg), .iereg(iereg), .iireg(iireg), .lcreg(lcreg), .lsreg(lsreg), .mcreg(mcreg), .msreg(msreg), .sreg(sreg), .ena_ier(ena_ier), .ena_lcr(ena_lcr), .ena_mcr(ena_mcr), .ena_sr(ena_sr), .read_msr(read_msr), .read_iir(read_iir), .read_lsr(read_lsr), .write_thr(write_thr), .write_dlr(write_dlr), .write_dmr(write_dmr), .ddis(ddis), .d(dout));    uart_reg u_uart_reg (.clk(clk), .wr(wr), .mr(mr), .rd(rd), .write_thr(write_thr), .write_dlr(write_dlr), .write_dmr(write_dmr), .ena_ier(ena_ier), .ena_lcr(ena_lcr), .ena_mcr(ena_mcr), .ena_sr(ena_sr), .read_msr(read_msr), .read_iir(read_iir), .prevrdlsr(prevrdlsr), .ctsn(ctsn), .dsrn(dsrn), .dcdn(dcdn), .rin(rin), .d(din), .lsreg_b0(lsreg_b0), .lsreg11(lsreg11), .lsreg_b3(lsreg_b3), .lsreg_b2(lsreg_b2), .lsreg_b4(lsreg_b4), .lsreg51(lsreg51), .lsreg_b7(lsreg_b7), .temt(temt), .sin(sin), .thrint(thrint), .sout_org(sout_org), .thrint4(thrint4), .thrint5(thrint5), .sin_org(sin_org), .dmreg(dmreg), .dlreg(dlreg), .iereg(iereg), .lcreg(lcreg), .lsreg(lsreg), .mcreg(mcreg), .msreg(msreg), .fcreg(fcreg), .fcreg11(fcreg11), .fcreg21(fcreg21), .rtsn(rtsn), .dtrn(dtrn), .out1n(out1n), .out2n(out2n), .sout(sout), .sreg(sreg));    intcontrol u_intcontrol (.mr(mr), .rd(rd), .wr(wr), .toint1(toint1), .at_trig_level(at_trig_level), .topre(topre), .rbrint(rbrint), .rbrint1(rbrint1), .thrint(thrint), .thrint1(thrint1), .thrint4(thrint4), .thrint5(thrint5), .read_iir(read_iir), .write_thr(write_thr), .toint(toint), .topre2(topre2), .lsreg(lsreg), .msreg(msreg[3:0]), .iereg(iereg), .intr(intr), .iireg(iireg));    baudgen u_baudgen (.clk(clk), .mr(mr), .dlreg(dlreg), .dmreg(dmreg), .baudoutn(baudoutn), .txbaud(txbaud));    txblock u_txblock (.clk(clk), .mr(mr), .thrint(thrint), .thrint1(thrint1), .txfifo_empty(txfifo_empty), .txfifo_2char(txfifo_2char), .lsreg_b5(lsreg[5]), .fcreg_b0(fcreg[0]), .lcreg(lcreg[6:0]), .threg(threg), .txbaud(txbaud), .read_txfifo(read_txfifo), .temt(temt), .sout_org(sout_org));    rxblock u_rxblock (.rclk(rclk), .mr(mr), .lcreg(lcreg[5:0]), .lsreg(lsreg[6:0]), .topre2(topre2), .toint(toint), .fcreg(fcreg), .rxfifo_full(rxfifo_full), .rxfifo_empty(rxfifo_empty), .toint1(toint1), .topre(topre), .lsreg11(lsreg11), .sin_org(sin_org), .rxf(rxf), .write_rxfifo(write_rxfifo));    fifoctrl u_fifoctrl (.rclk(rclk), .clk(clk), .rd(rd), .wr(wr), .rbrint(rbrint), .mr(mr), .write_rxfifo(write_rxfifo), .read_txfifo(read_txfifo), .write_thr(write_thr), .read_lsr(read_lsr), .d(din), .fcreg(fcreg), .rxf(rxf), .lsreg(lsreg), .prevrdlsr(prevrdlsr), .at_trig_level(at_trig_level), .rbrint1(rbrint1), .fcreg11(fcreg11), .fcreg21(fcreg21), .lsreg_b2(lsreg_b2), .lsreg_b3(lsreg_b3), .lsreg_b4(lsreg_b4), .lsreg_b0(lsreg_b0), .lsreg51(lsreg51), .lsreg_b7(lsreg_b7), .txfifo_empty(txfifo_empty), .txfifo_2char(txfifo_2char), .rxfifo_full(rxfifo_full), .rxfifo_empty(rxfifo_empty), .rxrdyn(rxrdyn), .txrdyn(txrdyn), .rbreg(rbreg), .threg(threg)); endmodule