-- smbus.vhd
--
-- Created: 6/14/00 JRH
--
-- 	This code has been started from a copy of the Xilinx I2C code referred to in XAPP333 and created 
--	by ALS.  The original code implements the control of the smbus bus with a MC68000 type interface. 
--	It is modeled from the M-bus component in certain Motorola uC.
--	The SMBUS control is done in the component smbus_control and the uC interface is implemented
--	in the component uC_interface. This file does not contain any logic descriptions, it simply
--	instantiates the two components and hooks them together.
--
-- Revised: 6/20/00 JRH
--	Added rsta_rst signal to facilitate resetting the rsta bit in the uC once the repeated
--	start transition has been completed by the SMBUS master.
-- Revised: 6/26/00 ALS
--	Changed declaration and instantiation of uc_interface component to reflect change
--	to Hitachi SH7750 processor.


library IEEE;
use IEEE.std_logic_1164.all;

entity smbus is 
  port (
		-- SMBUS bus signals
		sda	: inout	std_logic;		
		scl	: inout	std_logic;

		-- uC interface signals
		addr_bus	: in		std_logic_vector(7 downto 0);
		data_bus	: inout		std_logic_vector(7 downto 0);
		cs_n		: in		std_logic;	-- chip_select, active low
		bs_n		: in		std_logic;	-- bus select, active low
		rd_n		: in		std_logic;	-- read enable, active low
		we_n		: in		std_logic;	-- write enable, active low
		rd_wrn		: in		std_logic;	-- active high read, active low write
		rdy_n		: out		std_logic;	-- active low ready signal
		irq		: out		std_logic;	-- interrupt request
		
		mcf		: inout		std_logic;  -- temporary output for testing 


		-- clock and reset
		clk		: in		std_logic;
		reset		: in		std_logic
	);
end smbus;
		
library IEEE;
use IEEE.std_logic_1164.all;

architecture behave of smbus is

-- ****************************** Component Definitions ****************************

-- Define the SMBUS Control logic
component smbus_control 
  port(
	-- SMBUS bus signals
	sda : inout std_logic;
        scl : inout std_logic;
	
	-- interface signals from uP interface
	txak		: in		std_logic;	-- value for acknowledge when xmit
	msta		: in		std_logic; 	-- master/slave select
	msta_rst	: out		std_logic;	-- resets MSTA bit if arbitration is lost
	rsta		: in		std_logic;	-- repeated start 
	mtx		: in		std_logic;	-- master read/write 
	mbdr_micro	: in		std_logic_vector(7 downto 0);	-- uP data to output on SMBUS bus
	madr		: in		std_logic_vector(7 downto 0); -- SMBUS slave address
	mbb		: out		std_logic;	-- bus busy
	mcf		: inout		std_logic;	-- data transfer
	maas		: inout		std_logic;	-- addressed as slave
	mal		: inout		std_logic;	-- arbitration lost
	srw		: inout		std_logic;	-- slave read/write
	mif		: out		std_logic; 	-- interrupt pending
	rxak		: out		std_logic;	-- received acknowledge
	mbdr_smbus	: inout		std_logic_vector(7 downto 0); -- SMBUS data for uP
	mbcr_wr		: in		std_logic;	-- indicates that MCBR register was written
	mif_bit_reset 	: in		std_logic;	-- indicates that the MIF bit should be reset
	mal_bit_reset 	: in		std_logic;	-- indicates that the MAL bit should be reset
	men_bit_reset 	: out		std_logic;	-- indicates that the MEN bit should be reset
	rsta_rst	: out		std_logic;  -- smbus controller modifies rsta in uc


      	sys_clk 	: in 		std_logic;
	reset 		: in 		std_logic);

end component;

-- Define the uC interface
component uc_interface 
	port(
		-- 68000 parallel bus interface
		clk		: in STD_LOGIC;
		reset 	: in STD_LOGIC;	 
		
		addr_bus	: in STD_LOGIC_VECTOR (7 downto 0);
		data_bus	: inout STD_LOGIC_VECTOR (7 downto 0);
		cs_n 		: in STD_LOGIC; 	-- chip select, active low	
		bs_n 		: in STD_LOGIC; 	-- bus select, active low
		
		-- Directional pins
		rd_n		: in STD_LOGIC;		-- read enable, active low 
		we_n		: in STD_LOGIC; 	-- write enable, active low
		rd_wrn		: in STD_LOGIC;		-- active high read, active low write
		rdy_n		: out STD_LOGIC;	-- active low ready signal
		irq		: out STD_LOGIC;	-- Interrupt request
	
		-- Internal SMBUS Bus Registers
		-- Address Register (Contains slave address)
		madr	      : inout STD_LOGIC_VECTOR(7 downto 0);
   
                -- Control Register		
		men             : inout STD_LOGIC;  -- SMBUS Enable bit
		mien            : inout STD_LOGIC;	-- interrupt enable
		msta            : inout STD_LOGIC;	-- Master/Slave bit
		mtx             : inout STD_LOGIC;	-- Master read/write
		txak            : inout STD_LOGIC;	-- acknowledge bit
		rsta            : inout STD_LOGIC;	-- repeated start
	
		mbcr_wr         : out STD_LOGIC;	-- indicates that the control reg has been written
		rsta_rst	    : in  STD_LOGIC;	-- signal from msbus controller to modify rsta

                -- Status Register
		mcf             : in STD_LOGIC;	-- end of data transfer
		maas            : in STD_LOGIC;	-- addressed as slave
		mbb             : in STD_LOGIC;	-- bus busy
		mal             : in STD_LOGIC;	-- arbitration lost
		srw             : in STD_LOGIC;	-- slave read/write
		mif             : in STD_LOGIC;	-- interrupt pending
		rxak            : in STD_LOGIC;	-- received acknowledge

		mal_bit_reset   : out STD_LOGIC;	-- indicates that the MAL bit should be reset
		mif_bit_reset   : out STD_LOGIC;	-- indicates that the MIF bit should be reset
		men_bit_reset   : in STD_LOGIC;		-- indicates that the MEN bit should be reset
		msta_rst	    : in STD_LOGIC;	-- resets the MSTA bit if arbitration is lost
		

                -- Data Register 
		mbdr_micro      : inout STD_LOGIC_VECTOR (7 downto 0);
		mbdr_smbus        : in STD_LOGIC_VECTOR (7 downto 0);

		mbdr_read       : out STD_LOGIC
		
		);
end component;

-- ****************************** Signal Declarations ****************************

-- control register
signal madr			: std_logic_vector(7 downto 0); -- SMBUS address
signal men			: std_logic;		-- smbus enable - used as smbus reset
signal mien			: std_logic;		-- interrupt enable
signal msta			: std_logic;		-- smbus master/slave select
signal mtx			: std_logic;		-- master read/write
signal txak			: std_logic;		-- value of acknowledge to be transmitted
signal rsta			: std_logic;		-- generate a repeated start
signal rsta_rst		: std_logic;		-- signal from smbus controller to modify rsta
signal mbcr_wr		: std_logic;		-- indicates the uC has written the MBCR

-- status register
--signal mcf			: std_logic;		-- indicates a completed data byte transfer
signal maas			: std_logic;		-- indicates the chip has been addressed as SMBus slave
signal mbb			: std_logic;		-- indicates the smbus bus is busy
signal mal			: std_logic;		-- indicates that arbitration for the smbus bus is lost
signal srw			: std_logic;		-- slave read/write
signal mif			: std_logic;		-- interrupt pending
signal rxak			: std_logic;		-- value of received acknowledge

-- resets for certain status and control register bits
signal mal_bit_reset	: std_logic;		-- resets arbitration lost indicator 
signal mif_bit_reset	: std_logic;		-- resets interrupt pending bit
signal men_bit_reset	: std_logic;		-- resets smbus controller enable bit
signal msta_rst		: std_logic;		-- resets master/slave select when arbitration is lost

-- data registers
-- there are two data registers, one to hold the uC data when the chip is transmitting on SMBUS
-- and one to hold the SMBUS data when the chip is receiving. This allows the two registers to 
-- be clocked by different clocks
signal mbdr_micro		: std_logic_vector(7 downto 0); -- uC data register
signal mbdr_smbus		: std_logic_vector(7 downto 0); -- smbus data register

signal mbdr_read		: std_logic;		-- indicates the mbdr_smbus register has been
								-- read by the uC

begin

-- ****************************** Component Instantiations ****************************
 
-- Instantiate the SMBUS Controller and connect it

SMBUS_CTRL: smbus_control

	port map (
			-- SMBUS bus signals
			sda => sda,
      			scl => scl,
	
			-- interface signals from uP interface
			txak		=> txak,
			msta		=> msta,
			msta_rst	=> msta_rst,
			rsta		=> rsta,
			rsta_rst	=> rsta_rst,
			mtx		=> mtx,
			mbdr_micro	=> mbdr_micro,
			madr		=> madr,
			mbb		=> mbb,
			mcf		=> mcf,
			maas		=> maas,
			mal		=> mal,
			srw		=> srw,
			mif		=> mif,
			rxak		=> rxak,
			mbdr_smbus	=> mbdr_smbus,
			mbcr_wr		=> mbcr_wr,
			mif_bit_reset 	=> mif_bit_reset,
			mal_bit_reset 	=> mal_bit_reset,
			men_bit_reset 	=> men_bit_reset,

      			sys_clk 	=> clk,
			reset 		=> men 
		);

-- Instantiate the uC interface and connect it

uC_CTRL: uc_interface 
	port map(
		-- 68000 parallel bus interface
		clk		=> clk,
		reset 		=> reset,	 
		
		addr_bus	=> addr_bus,
		data_bus	=> data_bus,
		cs_n 		=> cs_n,	
		bs_n 		=> bs_n,
		
		-- Directional pins
		rd_n		=> rd_n,
		we_n 		=> we_n, 
		rd_wrn		=> rd_wrn,
		rdy_n		=> rdy_n,
		irq		=> irq,
	
		-- Internal SMBUS Bus Registers
		-- Address Register (Contains slave address)
		madr	      => madr,

                -- Control Register		
		men		=> men,
		mien        	=> mien,
		msta        	=> msta,
		mtx         	=> mtx,
		txak        	=> txak,
		rsta        	=> rsta,
		rsta_rst	=> rsta_rst,
	
		mbcr_wr     	=> mbcr_wr,

                -- Status Register
		mcf             => mcf,
		maas            => maas,
		mbb             => mbb,
		mal             => mal,
		srw             => srw,
		mif             => mif,
		rxak            => rxak,

		mal_bit_reset   => mal_bit_reset,
		mif_bit_reset   => mif_bit_reset,
		men_bit_reset   => men_bit_reset,
		msta_rst	=> msta_rst,
		

                -- Data Register 
		mbdr_micro      => mbdr_micro,
		mbdr_smbus      => mbdr_smbus,

		mbdr_read       => mbdr_read
		
		);
		

end behave;