wire RD;
input CE;
wire CE;
input CLK;
wire CLK;
input MSR_EN;
wire MSR_EN;
input INIT;
wire INIT;
input INPUT;
wire INPUT;
output OUTPUT;
wire OUTPUT;
output DELTA_OUTPUT;
wire DELTA_OUTPUT;


wire INPUT_CHANGED_RESET;
wire RESET_INPUT_CHANGED_RESET;
reg OLD_VALUE;
reg RESET_INPUT_CHANGED;
reg INPUT_CHANGED;
reg REGISTERED_INPUT;

	always @(posedge CLK or negedge RESET)
		if (RESET == 1'b0)
			REGISTERED_INPUT <= 1'b0;
		else if (CE == 1'b1)
			REGISTERED_INPUT <= INPUT;

	always @(posedge CLK or negedge RESET)
		if (RESET == 1'b0)
			OLD_VALUE <= 1'b0;
		else if (CE == 1'b1)
			OLD_VALUE <= REGISTERED_INPUT;

	assign RESET_INPUT_CHANGED_RESET = ((RESET == 1'b0) || (INPUT_CHANGED == 1'b0)) ? 1'b1 : 1'b0;

	always @(posedge CLK or posedge RESET_INPUT_CHANGED_RESET)
		if (RESET_INPUT_CHANGED_RESET == 1'b1)
			RESET_INPUT_CHANGED <= 1'b0;
		else
			RESET_INPUT_CHANGED <= MSR_EN;

	assign INPUT_CHANGED_RESET = ((RESET == 1'b0) || (RESET_INPUT_CHANGED == 1'b1)) ? 1'b1 : 1'b0;

	always @(posedge CLK or posedge INPUT_CHANGED_RESET)
		if (INPUT_CHANGED_RESET == 1'b1)
			INPUT_CHANGED <= 1'b0;
		else if (CE == 1'b1)
			INPUT_CHANGED <= !INIT && (INPUT_CHANGED || (OLD_VALUE ^ REGISTERED_INPUT));

	assign OUTPUT = REGISTERED_INPUT;

	assign DELTA_OUTPUT = INPUT_CHANGED;

endmodule

module ModemControlLogic (CLK, RESET, CE, WR, RD, DATA_IN, RTS, DTR, OUT1,
		OUT2, CTS, DSR, DCD, RI, MCR_EN, MSR_EN, LOOPBACK, MODEM_CONTROL_INTERRUPT,
		MCR_OUT, MSR_OUT);

input CLK;
wire CLK;
input RESET;
wire RESET;
input CE;
wire CE;
input WR;
wire WR;
input RD;
wire RD;
input [7:0] DATA_IN;
wire [7:0] DATA_IN;
output RTS;
wire RTS;
output DTR;
wire DTR;
output OUT1;
wire OUT1;
output OUT2;
wire OUT2;
input CTS;
wire CTS;
input DSR;
wire DSR;
input DCD;
wire DCD;
input RI;
wire RI;
input MCR_EN;
wire MCR_EN;
input MSR_EN;
wire MSR_EN;
output LOOPBACK;
wire LOOPBACK;
output MODEM_CONTROL_INTERRUPT;
wire MODEM_CONTROL_INTERRUPT;
output [4:0] MCR_OUT;
wire [4:0] MCR_OUT;
output [7:0] MSR_OUT;
wire [7:0] MSR_OUT;


reg MCR_4;
reg MCR_3;
reg MCR_2;
reg MCR_1;
reg MCR_0;
wire CTS_CHANGED;
wire DSR_CHANGED;
wire DCD_CHANGED;
reg RI_CHANGED;
wire RI_CHANGED_RESET;
reg RESET_RI_CHANGED;
wire RESET_RI_CHANGED_RESET;

wire CTS_TEMP;
wire DSR_TEMP;
wire DCD_TEMP;
wire RI_TEMP;

wire CTS_REG;
wire DSR_REG;
wire DCD_REG;
reg RI_REG;

reg RI_OLD_VALUE;
reg [1:0] INITIALIZE_CHANGE_DETECTORS;

	always @(posedge WR or negedge RESET)
		if (RESET == 0)
		begin
			MCR_4 <= 1'b0;
			MCR_3 <= 1'b0;
			MCR_2 <= 1'b0;
			MCR_1 <= 1'b0;
			MCR_0 <= 1'b0;
		end
		else if (MCR_EN == 1'b1)
		begin
			MCR_4 <= DATA_IN[4];
			MCR_3 <= DATA_IN[3];
			MCR_2 <= DATA_IN[2];
			MCR_1 <= DATA_IN[1];
			MCR_0 <= DATA_IN[0];
		end

	assign LOOPBACK = MCR_4;

	assign MCR_OUT = {MCR_4, MCR_3, MCR_2, MCR_1, MCR_0};

	assign DTR = (MCR_4 == 1'b0) ? !MCR_0 : 1'b1;
	assign RTS = (MCR_4 == 1'b0) ? !MCR_1 : 1'b1;
	assign OUT1 = (MCR_4 == 1'b0) ? !MCR_2 : 1'b1;
	assign OUT2 = (MCR_4 == 1'b0) ? !MCR_3 : 1'b1;

	assign DCD_TEMP = (MCR_4 == 1'b0) ? !DCD : MCR_3;
	assign RI_TEMP = (MCR_4 == 1'b0) ? !RI : MCR_2;
	assign DSR_TEMP = (MCR_4 == 1'b0) ? !DSR : MCR_1;
	assign CTS_TEMP = (MCR_4 == 1'b0) ? !CTS : MCR_0;

	always @(posedge CLK or negedge RESET)
		if (RESET == 1'b0)
			INITIALIZE_CHANGE_DETECTORS <= 2'b11;
		else if (CE == 1'b1)
			INITIALIZE_CHANGE_DETECTORS <= {INITIALIZE_CHANGE_DETECTORS[0], 1'b0};

	ChangeDetector U0(
		.INPUT(DCD_TEMP),
		.RESET(RESET),
		.RD(RD),
		.MSR_EN(MSR_EN),
		.CLK(CLK),
		.CE(CE),
		.INIT(INITIALIZE_CHANGE_DETECTORS[1]),
		.OUTPUT(DCD_REG),
		.DELTA_OUTPUT(DCD_CHANGED)
	);

	ChangeDetector U1(
		.INPUT(DSR_TEMP),
		.RESET(RESET),
		.RD(RD),
		.MSR_EN(MSR_EN),
		.CLK(CLK),
		.CE(CE),
		.INIT(INITIALIZE_CHANGE_DETECTORS[1]),
		.OUTPUT(DSR_REG),
		.DELTA_OUTPUT(DSR_CHANGED)
		);

	ChangeDetector U2(
		.INPUT(CTS_TEMP),
		.RESET(RESET),
		.RD(RD),
		.MSR_EN(MSR_EN),
		.CLK(CLK),
		.CE(CE),
		.INIT(INITIALIZE_CHANGE_DETECTORS[1]),
		.OUTPUT(CTS_REG),
		.DELTA_OUTPUT(CTS_CHANGED)
		);

	always @(posedge CLK or negedge RESET)
		if (RESET == 1'b0)
			RI_REG <= 1'b0;
		else if (CE == 1'b1)
			RI_REG <= RI_TEMP;

	assign RI_CHANGED_RESET = ((RESET == 1'b0) || (RESET_RI_CHANGED == 1'b1)) ? 1'b1 : 1'b0;

	always @(posedge CLK or posedge RI_CHANGED_RESET)
		if (RI_CHANGED_RESET == 1'b1)
			RI_CHANGED <= 1'b0;
		else if (CE == 1'b1)
			RI_CHANGED <= !INITIALIZE_CHANGE_DETECTORS[1] && (RI_CHANGED || (RI_OLD_VALUE && !RI_REG));

	always @(posedge CLK or negedge RESET)
		if (RESET == 1'b0)
			RI_OLD_VALUE <= 1'b0;
		else if (CE == 1'b1)
			RI_OLD_VALUE <= RI_REG;

	assign RESET_RI_CHANGED_RESET = ((RESET == 1'b0) || (RI_CHANGED == 1'b0)) ? 1'b1 : 1'b0;

	always @(posedge RD or posedge RESET_RI_CHANGED_RESET)
		if (RESET_RI_CHANGED_RESET == 1'b1)
			RESET_RI_CHANGED <= 1'b0;
		else
			RESET_RI_CHANGED <= MSR_EN;

	
	assign MSR_OUT[7] = DCD_REG;
	assign MSR_OUT[6] = RI_REG;
	assign MSR_OUT[5] = DSR_REG;
	assign MSR_OUT[4] = CTS_REG;
	assign MSR_OUT[3] = DCD_CHANGED;
	assign MSR_OUT[2] = RI_CHANGED;
	assign MSR_OUT[1] = DSR_CHANGED;
	assign MSR_OUT[0] = CTS_CHANGED;

	assign MODEM_CONTROL_INTERRUPT = DCD_CHANGED || RI_CHANGED || DSR_CHANGED || CTS_CHANGED;

endmodule

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {C_16450}}

module C_16450 (CLK, RD, WR, CE, MR, CS0, CS1, CS2, CSOUT, CTS, DCD, DSR,
		RI, A, DATA_IN, DDIS, INT, SIN, SOUT, DTR, OUT1, OUT2, RTS,
		DATA_OUT);

input CLK;
wire CLK;
input RD;
wire RD;
input WR;
wire WR;
input CE;
wire CE;
input MR;
wire MR;
input CS0;
wire CS0;
input CS1;
wire CS1;
input CS2;
wire CS2;
output CSOUT;
wire CSOUT;
input CTS;
wire CTS;
input DCD;
wire DCD;
input DSR;
wire DSR;
input RI;
wire RI;
input [2:0] A;
wire [2:0] A;
input [7:0] DATA_IN;
wire [7:0] DATA_IN;
output DDIS;
wire DDIS;
output INT;
wire INT;
input SIN;
wire SIN;
output SOUT;
wire SOUT;
output DTR;
wire DTR;
output OUT1;
wire OUT1;
output OUT2;
wire OUT2;
output RTS;
wire RTS;
output [7:0] DATA_OUT;
wire [7:0] DATA_OUT;


//}} End of automatically maintained section

wire [1:0] BITS_COUNT;
wire BREAK;
wire CONST_PARITY;
wire [15:0] DIV_VAL;
wire IER_EN;
wire [3:0] IER_OUT;
wire IID_EN;
wire [2:0] IID_OUT;
wire INTERNAL_SERIAL_OUT;
wire LINE_STATUS_INTERRUPT;
wire LOOPBACK;
wire LSR_EN;
wire [4:0] LSR_LSB;
wire [1:0] LSR_MSB;
wire MCR_EN;
wire [4:0] MCR_OUT;
wire MODEM_CONTROL_INTERRUPT;
wire MSR_EN;
wire [7:0] MSR_OUT;
wire PARITY_ENABLE;
wire PARITY_TYPE;
wire RECEIVER_INTERRUPT;
wire RHR_EN;
wire [7:0] RHR_OUT;
wire STOP_BITS;
wire THR_EN;
wire TRANSMITTER_CE;
wire TRANSMITTER_INTERRUPT;
wire TRANSMITTER_INTERRUPT_ACK;
wire RECEIVER_CE;


	Registers U0(
		.CS0(CS0),
		.CS1(CS1),
		.CS2(CS2),
		.CSOUT(CSOUT),
		.DDIS(DDIS),
		.A(A),
		.RESET(MR),
		.THR_EN(THR_EN),
		.RHR_EN(RHR_EN),
		.LSR_EN(LSR_EN),
		.IER_EN(IER_EN),
		.IID_EN(IID_EN),
		.MCR_EN(MCR_EN),
		.MSR_EN(MSR_EN),
		.WR(WR),
		.RD(RD),
		.DATA_IN(DATA_IN),
		.DATA_OUT(DATA_OUT),
		.DIV_REG_OUT(DIV_VAL),
		.WORD_LEN(BITS_COUNT),
		.RHR(RHR_OUT),
		.MCR(MCR_OUT),
		.MSR(MSR_OUT),
		.LSR_LSB(LSR_LSB),
		.LSR_MSB(LSR_MSB),
		.IER(IER_OUT),
		.IID(IID_OUT),
		.BREAK(BREAK),
		.STOP_BITS(STOP_BITS),
		.STICK_PARITY(CONST_PARITY),
		.PARITY_EVEN_nODD(PARITY_TYPE),
		.PARITY_ENABLE(PARITY_ENABLE)
	);

	BaudGenerator U1(
		.RESET(MR),
		.CE(CE),
		.CE_OUT(RECEIVER_CE),
		.TRANSMITTER_CE(TRANSMITTER_CE),
		.DIV_VAL(DIV_VAL),
		.CLK(CLK)
	);

	ReceiverCore U2(
		.CLK(CLK),
		.RESET(MR),
		.CE(RECEIVER_CE),
		.LOOPBACK(LOOPBACK),
		.EXTERNAL_SERIAL_IN(SIN),
		.INTERNAL_SERIAL_IN(INTERNAL_SERIAL_OUT),
		.RHR_OUT(RHR_OUT),
		.LSR_OUT(LSR_LSB),
		.BITS_COUNT(BITS_COUNT),
		.PARITY_ENABLE(PARITY_ENABLE),
		.PARITY_EVEN_nODD(PARITY_TYPE),
		.STICK_PARITY(CONST_PARITY),
		.RD(RD),
		.LINE_STATUS_INTERRUPT(LINE_STATUS_INTERRUPT),
		.RECEIVER_INTERRUPT(RECEIVER_INTERRUPT),
		.RHR_EN(RHR_EN),
		.LSR_EN(LSR_EN)
	);

	TransmitterCore U3(
		.CLK(CLK),
		.RESET(MR),
		.CE(TRANSMITTER_CE),
		.BREAK(BREAK),
		.LOOPBACK(LOOPBACK),
		.DATA_IN(DATA_IN),
		.RD(RD),
		.WR(WR),
		.THR_EN(THR_EN),
		.IID_EN(IID_EN),
		.SERIAL_OUT(SOUT),
		.INTERNAL_SO(INTERNAL_SERIAL_OUT),
		.BITS_COUNT(BITS_COUNT),
		.PARITY_ENABLE(PARITY_ENABLE),
		.PARITY_EVEN_nODD(PARITY_TYPE),
		.STICK_PARITY(CONST_PARITY),
		.TRANSMITTER_INTERRUPT_ACK(TRANSMITTER_INTERRUPT_ACK),
		.TRANSMITTER_INTERRUPT(TRANSMITTER_INTERRUPT),
		.LSR_MSB(LSR_MSB),
		.STOP_BITS(STOP_BITS)
	);

	InterruptControlLogic U4(
		.CLK(CLK),
		.RESET(MR),
		.CE(CE),
		.RD(RD),
		.WR(WR),
		.DATA_IN(DATA_IN),
		.IER_EN(IER_EN),
		.IID_EN(IID_EN),
		.IER_OUT(IER_OUT),
		.IID_OUT(IID_OUT),
		.TRANSMITTER_INTERRUPT(TRANSMITTER_INTERRUPT),
		.TRANSMITTER_INTERRUPT_ACK(TRANSMITTER_INTERRUPT_ACK),
		.RECEIVER_INTERRUPT(RECEIVER_INTERRUPT),
		.LINE_STATUS_INTERRUPT(LINE_STATUS_INTERRUPT),
		.MODEM_CONTROL_INTERRUPT(MODEM_CONTROL_INTERRUPT),
		.INTERRUPT(INT)
	);

	ModemControlLogic U5(
		.CLK(CLK),
		.RESET(MR),
		.CE(CE),
		.WR(WR),
		.RD(RD),
		.DATA_IN(DATA_IN),
		.RTS(RTS),
		.DTR(DTR),
		.OUT1(OUT1),
		.OUT2(OUT2),
		.CTS(CTS),
		.DSR(DSR),
		.DCD(DCD),
		.RI(RI),
		.MCR_EN(MCR_EN),
		.MSR_EN(MSR_EN),
		.LOOPBACK(LOOPBACK),
		.MODEM_CONTROL_INTERRUPT(MODEM_CONTROL_INTERRUPT),
		.MCR_OUT(MCR_OUT),
		.MSR_OUT(MSR_OUT)
	);

endmodule
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