{ "Info" "IFYGR_FYGR_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that use the same VCCIO and VREF " "Info: Statistics of I/O pins that use the same VCCIO and VREF" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "7 unused 3.30 0 7 0 " "Info: Number of I/O pins in group: 7 (unused VREF, 3.30 VCCIO, 0 input, 7 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: Details of I/O bank before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 5 15 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 5 total pin(s) used --  15 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 24 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 8 20 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 8 total pin(s) used --  20 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "after " "Info: Details of I/O bank after I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 12 8 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 12 total pin(s) used --  8 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 24 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 8 20 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 8 total pin(s) used --  20 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Warning" "WCDB_CDB_UNATTACHED_ASGN" "" "Warning: Following nodes are assigned to locations or regions, but do not exist in design" { { "Warning" "WCDB_CDB_UNATTACHED_ASGN_SUB" "CO " "Warning: Node CO is assigned to location or region, but does not exist in design" {  } { { "f:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "f:/quartus/bin/Assignment Editor.qase" 0 { { 0 "CO" } } } }  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.535 ns register register " "Info: Estimated most critical path is register to register delay of 3.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns COUNT_16:u1\|lpm_counter:CQI_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[6\] 1 REG LAB_X5_Y2 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y2; Fanout = 12; REG Node = 'COUNT_16:u1\|lpm_counter:CQI_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[6\]'" {  } { { "C:/Documents and Settings/鄭崢/桌面/COUNT_100/復件 ASDF/復件 ASDF/db/COUNT_16_7_cmp.qrpt" "" "" { Report "C:/Documents and Settings/鄭崢/桌面/COUNT_100/復件 ASDF/復件 ASDF/db/COUNT_16_7_cmp.qrpt" Compiler "COUNT_16_7" "UNKNOWN" "V1" "C:/Documents and Settings/鄭崢/桌面/COUNT_100/復件 ASDF/復件 ASDF/db/COUNT_16_7.quartus_db" { Floorplan "" "" "" { COUNT_16:u1|lpm_counter:CQI_rtl_0|alt_counter_stratix:wysi_counter|safe_q[6] } "NODE_NAME" } } } { "f:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "f:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.519 ns) + CELL(0.442 ns) 0.961 ns COUNT_16:u1\|i~145 2 COMB LAB_X4_Y2 1 " "Info: 2: + IC(0.519 ns) + CELL(0.442 ns) = 0.961 ns; Loc. = LAB_X4_Y2; Fanout = 1; COMB Node = 'COUNT_16:u1\|i~145'" {  } { { "C:/Documents and Settings/鄭崢/桌面/COUNT_100/復件 ASDF/復件 ASDF/db/COUNT_16_7_cmp.qrpt" "" "" { Report "C:/Documents and Settings/鄭崢/桌面/COUNT_100/復件 ASDF/復件 ASDF/db/COUNT_16_7_cmp.qrpt" Compiler "COUNT_16_7" "UNKNOWN" "V1" "C:/Documents and Settings/鄭崢/桌面/COUNT_100/復件 ASDF/復件 ASDF/db/COUNT_16_7.quartus_db" { Floorplan "" "" "0.961 ns" { COUNT_16:u1|lpm_counter:CQI_rtl_0|alt_counter_stratix:wysi_counter|safe_q[6] COUNT_16:u1|i~145 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.292 ns) 1.922 ns COUNT_16:u1\|i~142 3 COMB LAB_X5_Y2 8 " "Info: 3: + IC(0.669 ns) + CELL(0.292 ns) = 1.922 ns; Loc. = LAB_X5_Y2; Fanout = 8; COMB Node = 'COUNT_16:u1\|i~142'" {  } { { "C:/Documents and Settings/鄭崢/桌面/COUNT_100/復件 ASDF/復件 ASDF/db/COUNT_16_7_cmp.qrpt" "" "" { Report "C:/Documents and Settings/鄭崢/桌面/COUNT_100/復件 ASDF/復件 ASDF/db/COUNT_16_7_cmp.qrpt" Compiler "COUNT_16_7" "UNKNOWN" "V1" "C:/Documents and Settings/鄭崢/桌面/COUNT_100/復件 ASDF/復件 ASDF/db/COUNT_16_7.quartus_db" { Floorplan "" "" "0.961 ns" { COUNT_16:u1|i~145 COUNT_16:u1|i~142 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.501 ns) + CELL(1.112 ns) 3.535 ns COUNT_16:u1\|lpm_counter:CQI_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[7\] 4 REG LAB_X5_Y2 10 " "Info: 4: + IC(0.501 ns) + CELL(1.112 ns) = 3.535 ns; Loc. = LAB_X5_Y2; Fanout = 10; REG Node = 'COUNT_16:u1\|lpm_counter:CQI_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[7\]'" {  } { { "C:/Documents and Settings/鄭崢/桌面/COUNT_100/復件 ASDF/復件 ASDF/db/COUNT_16_7_cmp.qrpt" "" "" { Report "C:/Documents and Settings/鄭崢/桌面/COUNT_100/復件 ASDF/復件 ASDF/db/COUNT_16_7_cmp.qrpt" Compiler "COUNT_16_7" "UNKNOWN" "V1" "C:/Documents and Settings/鄭崢/桌面/COUNT_100/復件 ASDF/復件 ASDF/db/COUNT_16_7.quartus_db" { Floorplan "" "" "1.613 ns" { COUNT_16:u1|i~142 COUNT_16:u1|lpm_counter:CQI_rtl_0|alt_counter_stratix:wysi_counter|safe_q[7] } "NODE_NAME" } } } { "f:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "f:/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.846 ns 52.22 % " "Info: Total cell delay = 1.846 ns ( 52.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.689 ns 47.78 % " "Info: Total interconnect delay = 1.689 ns ( 47.78 % )" {  } {  } 0}  } { { "C:/Documents and Settings/鄭崢/桌面/COUNT_100/復件 ASDF/復件 ASDF/db/COUNT_16_7_cmp.qrpt" "" "" { Report "C:/Documents and Settings/鄭崢/桌面/COUNT_100/復件 ASDF/復件 ASDF/db/COUNT_16_7_cmp.qrpt" Compiler "COUNT_16_7" "UNKNOWN" "V1" "C:/Documents and Settings/鄭崢/桌面/COUNT_100/復件 ASDF/復件 ASDF/db/COUNT_16_7.quartus_db" { Floorplan "" "" "3.535 ns" { COUNT_16:u1|lpm_counter:CQI_rtl_0|alt_counter_stratix:wysi_counter|safe_q[6] COUNT_16:u1|i~145 COUNT_16:u1|i~142 COUNT_16:u1|lpm_counter:CQI_rtl_0|alt_counter_stratix:wysi_counter|safe_q[7] } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 24 16:58:33 2005 " "Info: Processing ended: Thu Nov 24 16:58:33 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}