library verilog;use verilog.vl_types.all;entity hdl_demo is    port(        rst             : in     vl_logic;        clk             : in     vl_logic;        start_value     : in     vl_logic_vector(31 downto 0);        in_a            : in     vl_logic;        in_b            : in     vl_logic;        in_c            : in     vl_logic;        accum_a         : in     vl_logic_vector(7 downto 0);        accum_b         : in     vl_logic_vector(7 downto 0);        result          : out    vl_logic_vector(7 downto 0)    );end hdl_demo;