library verilog;use verilog.vl_types.all;entity alu is    port(        clk             : in     vl_logic;        a               : in     vl_logic_vector(7 downto 0);        b               : in     vl_logic_vector(7 downto 0);        opcode          : in     vl_logic_vector(2 downto 0);        outp_a          : out    vl_logic_vector(7 downto 0);        outp_s          : out    vl_logic_vector(7 downto 0)    );end alu;