?? alu.tlg
字號:
Selecting top level module alu
Synthesizing module alu
@W:"J:\Project_Navigator_Demo\alu_vlog\ALU.V":28:4:28:7|Latch generated from always block for signal outp_a[7:0], probably caused by a missing assignment in an if or case stmt
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -