?? alu.srr
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$ Start of Compile
#Fri Nov 08 09:10:18 2002
Synplicity Verilog Compiler, version 7.0.0, Build 130R, built Nov 16 2001
Copyright (C) 1994-2001, Synplicity Inc. All Rights Reserved
@I::"J:\Project_Navigator_Demo\alu_vlog\ALU.V"
Verilog syntax check successful!
File J:\Project_Navigator_Demo\alu_vlog\ALU.V changed - recompiling
Selecting top level module alu
Synthesizing module alu
@W:"J:\Project_Navigator_Demo\alu_vlog\ALU.V":28:4:28:7|Latch generated from always block for signal outp_a[7:0], probably caused by a missing assignment in an if or case stmt
@END
Process took 0.27 seconds realtime, 0.27 seconds cputime
Synplicity Xilinx Technology Mapper, version 7.0.0, Build 129R, built Nov 12 2001
Copyright (C) 1994-2001, Synplicity Inc. All Rights Reserved
Clock Buffers:
Inserting Clock buffer for port clk, TNM=clk
Net buffering Report for view:work.alu(verilog):
No nets needed buffering.
@N|The option to pack flops in the IOB has not been specified
Writing Analyst data base J:\Project_Navigator_Demo\alu_vlog\alu_vlog_syn1\ALU.srm
Writing EDIF Netlist and constraint files
Found clock clk with period 1000.00ns
@W:"j:\project_navigator_demo\alu_vlog\alu.v":1:1:33:6|Net un1_outp_a25_0 appears to be a clock source which was not identified. Assuming default frequency.
##### START TIMING REPORT #####
# Timing Report written on Fri Nov 08 09:10:21 2002
#
Top view: alu
Slew propagation mode: worst
Paths requested: 5
Constraint File(s):
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.
Performance Summary
*******************
Worst slack in design: 991.640
Requested Estimated Requested Estimated Clock
Starting Clock Frequency Frequency Period Period Slack Type
-----------------------------------------------------------------------------------------------
clk 1.0 MHz 357.1 MHz 1000.000 2.800 997.200 inferred
System 1.0 MHz 119.6 MHz 1000.000 8.360 991.640 system
===============================================================================================
Clock Relationships
*******************
Starting Ending r/r f/f r/f f/r
Clock Clock time (ns) time (ns) time (ns) time (ns)
---------------------------------------------------------------------------
clk clk 1000.0 - - -
===========================================================================
Interface Information
*********************
Input Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
---------------------------------------------------------------------------------
a[0] System (rising) NA 0.000 992.861 992.861
a[1] System (rising) NA 0.000 992.942 992.942
a[2] System (rising) NA 0.000 993.023 993.023
a[3] System (rising) NA 0.000 993.104 993.104
a[4] System (rising) NA 0.000 993.185 993.185
a[5] System (rising) NA 0.000 993.266 993.266
a[6] System (rising) NA 0.000 993.346 993.346
a[7] System (rising) NA 0.000 994.196 994.196
b[0] System (rising) NA 0.000 992.961 992.961
b[1] System (rising) NA 0.000 993.042 993.042
b[2] System (rising) NA 0.000 993.123 993.123
b[3] System (rising) NA 0.000 993.204 993.204
b[4] System (rising) NA 0.000 993.285 993.285
b[5] System (rising) NA 0.000 993.366 993.366
b[6] System (rising) NA 0.000 993.447 993.447
b[7] System (rising) NA 0.000 994.296 994.296
clk NA NA NA NA NA
opcode[0] System (rising) NA 0.000 991.640 991.640
opcode[1] System (rising) NA 0.000 995.446 995.446
opcode[2] System (rising) NA 0.000 991.640 991.640
=================================================================================
Output Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
---------------------------------------------------------------------------------
outp_a[0] System (rising) NA 5.600 1000.000 994.400
outp_a[1] System (rising) NA 5.600 1000.000 994.400
outp_a[2] System (rising) NA 5.600 1000.000 994.400
outp_a[3] System (rising) NA 5.600 1000.000 994.400
outp_a[4] System (rising) NA 5.600 1000.000 994.400
outp_a[5] System (rising) NA 5.600 1000.000 994.400
outp_a[6] System (rising) NA 5.600 1000.000 994.400
outp_a[7] System (rising) NA 5.600 1000.000 994.400
outp_s[0] clk (rising) NA 2.800 1000.000 997.200
outp_s[1] clk (rising) NA 2.800 1000.000 997.200
outp_s[2] clk (rising) NA 2.800 1000.000 997.200
outp_s[3] clk (rising) NA 2.800 1000.000 997.200
outp_s[4] clk (rising) NA 2.800 1000.000 997.200
outp_s[5] clk (rising) NA 2.800 1000.000 997.200
outp_s[6] clk (rising) NA 2.800 1000.000 997.200
outp_s[7] clk (rising) NA 2.800 1000.000 997.200
=================================================================================
====================================
Detailed Report for Clock: clk
====================================
Starting Points with worst slack
********************************
Arrival
Instance Type Pin Net Time Slack
------------------------------------------------------------------
outp_s[0] FD Q outp_s_c[0] 0.000 997.200
outp_s[1] FD Q outp_s_c[1] 0.000 997.200
outp_s[2] FD Q outp_s_c[2] 0.000 997.200
outp_s[3] FD Q outp_s_c[3] 0.000 997.200
outp_s[4] FD Q outp_s_c[4] 0.000 997.200
outp_s[5] FD Q outp_s_c[5] 0.000 997.200
outp_s[6] FD Q outp_s_c[6] 0.000 997.200
outp_s[7] FD Q outp_s_c[7] 0.000 997.200
==================================================================
Ending Points with worst slack
******************************
Required
Instance Type Pin Net Time Slack
-------------------------------------------------------------------------
outp_s[7:0] Port outp_s[0] outp_s[0] 1000.000 997.200
outp_s[7:0] Port outp_s[1] outp_s[1] 1000.000 997.200
outp_s[7:0] Port outp_s[2] outp_s[2] 1000.000 997.200
outp_s[7:0] Port outp_s[3] outp_s[3] 1000.000 997.200
outp_s[7:0] Port outp_s[4] outp_s[4] 1000.000 997.200
outp_s[7:0] Port outp_s[5] outp_s[5] 1000.000 997.200
outp_s[7:0] Port outp_s[6] outp_s[6] 1000.000 997.200
outp_s[7:0] Port outp_s[7] outp_s[7] 1000.000 997.200
=========================================================================
Worst Paths Information
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