LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY WERDTEST IS

PORT
	(   Rst:IN STD_LOGIC;
		WE_MCU:IN STD_lOGIC;
		RD_MCU:IN STD_LOGIC;
		CS1_MCU:IN STD_LOGIC;
		ADD_MCU: IN STD_LOGIC_VECTOR(13 DOWNTO 0);
        ADD_SRAM: OUT STD_LOGIC_VECTOR(12 DOWNTO 0);  --ADD_SRAM IS 32K SRAM, reserve 24k sram
        VIEDO_EN:OUT STD_LOGIC;
	    RD_MCU_1399B:OUT STD_LOGIC;
		WE_MCU_1399B:OUT STD_LOGIC;
		DATA_BUS_EN:OUT STD_LOGIC;
		DATA_BUS_DIR:OUT STD_LOGIC
		);	
END WERDTEST ;

ARCHITECTURE a OF WERDTEST  IS
 Begin 
PROCESS(RST,RD_MCU,CS1_MCU,ADD_MCU,WE_MCU)
 VARIABLE TemADD_MCU:STD_LOGIC_VECTOR(12 DOWNTO 0);
BEGIN

     TemADD_MCU(0):=ADD_MCU(0);
     TemADD_MCU(1):=ADD_MCU(1);
     TemADD_MCU(2):=ADD_MCU(2);
     TemADD_MCU(3):=ADD_MCU(3);
     TemADD_MCU(4):=ADD_MCU(4);
     TemADD_MCU(5):=ADD_MCU(5);
     TemADD_MCU(6):=ADD_MCU(6);
     TemADD_MCU(7):=ADD_MCU(7);
     TemADD_MCU(8):=ADD_MCU(8);
     TemADD_MCU(9):=ADD_MCU(9);
     TemADD_MCU(10):=ADD_MCU(10);
     TemADD_MCU(11):=ADD_MCU(11);
     TemADD_MCU(12):=ADD_MCU(12);
 IF RST='0' THEN
     VIEDO_EN<='1';
     RD_MCU_1399B<='1';
     WE_MCU_1399B<='1';
     DATA_BUS_EN<='1';
     DATA_BUS_DIR<='1';
     ADD_SRAM<="1111111111111";
 ELSIF(CS1_MCU='0' AND  ADD_MCU(13)='1' )THEN
     IF (WE_MCU='0' AND RD_MCU='1')THEN
        DATA_BUS_DIR<='0';
        DATA_BUS_EN<='0'; 
        WE_MCU_1399B<=WE_MCU;
     ELSE
        DATA_BUS_DIR<='1';
        DATA_BUS_EN<='0';
        RD_MCU_1399B<=RD_MCU;
     END IF;

     ADD_SRAM<=TemADD_MCU;
 ELSE
     ADD_SRAM<="1111111111111";
     RD_MCU_1399B<='1';
     WE_MCU_1399B<='1';
     DATA_BUS_EN<='1';
     DATA_BUS_DIR<='1';

 END IF;
		
END PROCESS;
END a;