--------------------------------------------------
-- Model        :   8051 Behavioral Model,
--                  VHDL Entity mc8051.osc_sm.interface
--
-- Author       :   Michael Mayer (mrmayer@computer.org),
--                  Dr. Hardy J. Pottinger,
--                  Department of Electrical Engineering
--                  University of Missouri - Rolla
--
-- Created at   :   09/22/98 13:45:05
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY mc8051 ;
USE mc8051.synth_pack.all;

ENTITY osc_sm IS
   PORT( 
      int_clk : IN     std_logic ;
      int_rst : IN     std_logic ;
      xtal1 : IN     std_logic ;
      cycle_states : OUT    std_logic_vector( 3 DOWNTO 0 )  ;
      xtal2 : OUT    std_logic
   );

-- Declarations

END osc_sm ;
--
-- VHDL Architecture mc8051.osc_sm.spec
--
-- Created:
--          by - mrmayer.UNKNOWN (eeultra5.ee.umr.edu)
--          at - 16:31:59 03/16/98
--
-- Generated by Mentor Graphics' Renoir(TM) 3.0 (Build 110)
--
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
 
ARCHITECTURE spec OF osc_sm IS
  SIGNAL state_reg : unsigned(3 DOWNTO 0);
BEGIN
  xtal2 <= NOT xtal1;
  state_reg <= "0000"        WHEN int_rst = '1' ELSE
               unsigned(s1p1) WHEN falling_edge(xtal1) AND 
                                   state_reg = unsigned(s6p2) ELSE 
               state_reg + 1 WHEN falling_edge(xtal1) ELSE
               state_reg;
  cycle_states <= std_logic_vector(state_reg);
END ARCHITECTURE spec;