--------------------------------------------------
-- Model        :   8051 Behavioral Model,
--                  VHDL Entity mc8051.tmp_regs.interface
--
-- Author       :   Michael Mayer (mrmayer@computer.org),
--                  Dr. Hardy J. Pottinger,
--                  Department of Electrical Engineering
--                  University of Missouri - Rolla
--
-- Created at   :   09/21/98 13:57:58
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY mc8051 ;
USE mc8051.cpu_pack.all;
USE mc8051.synth_pack.all;

ENTITY tmp_regs IS
   PORT( 
      acc : IN     std_logic_vector( 7 DOWNTO 0 )  ;
      acknow : IN     std_logic ;
      alu_result : IN     std_logic_vector( 7 DOWNTO 0 )  ;
      cpu_rst : IN     std_logic ;
      data_dest : IN     std_logic_vector( 2 DOWNTO 0 )  ;
      data_t1 : IN     std_logic_vector( 2 DOWNTO 0 )  ;
      data_t2 : IN     std_logic_vector( 2 DOWNTO 0 )  ;
      dest_cmd : IN     std_logic_vector( 3 DOWNTO 0 )  ;
      int_clk : IN     std_logic ;
      new_ir : IN     std_logic ;
      rs : IN     std_logic_vector( 1 DOWNTO 0 )  ;
      t1_cmd : IN     std_logic_vector( 3 DOWNTO 0 )  ;
      t2_cmd : IN     std_logic_vector( 3 DOWNTO 0 )  ;
      two_dests : IN     std_logic ;
      addr_gb : OUT    std_logic_vector( 7 DOWNTO 0 )  ;
      alu_second_result : OUT    std_logic ;
      bit_loc : OUT    std_logic_vector( 2 DOWNTO 0 )  ;
      cpu_done : OUT    std_logic ;
      dec_rd_sp : OUT    std_logic ;
      inc_wr_sp : OUT    std_logic ;
      indirect_sel : OUT    std_logic ;
      rd_gb : OUT    std_logic ;
      rd_pmem1 : OUT    std_logic ;
      rd_pmem2 : OUT    std_logic ;
      tmp1 : OUT    std_logic_vector( 7 DOWNTO 0 )  ;
      tmp1_done : OUT    std_logic ;
      tmp2 : OUT    std_logic_vector( 7 DOWNTO 0 )  ;
      wr_acc : OUT    std_logic ;
      wr_gb : OUT    std_logic ;
      wr_out : OUT    std_logic ;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 ) 
   );

-- Declarations

END tmp_regs ;
--
-- VHDL Architecture mc8051.tmp_regs.fsm
--
-- Created:
--          by - mrmayer.UNKNOWN (eceultra11.ece.umr.edu)
--          at - 13:57:58 09/21/98
--
-- Generated by Mentor Graphics' Renoir(TM) 3.4 (Build 18)
--
--
-- what will happen if I move this line in
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
LIBRARY mc8051 ;
USE mc8051.cpu_pack.all;

ARCHITECTURE fsm OF tmp_regs IS

   -- Architecture Declarations
   SIGNAL data_tmp : std_logic_vector(2 DOWNTO 0) ;
   SIGNAL t_cmd : std_logic_vector(3 DOWNTO 0) ;
   SIGNAL t1_active : std_logic ;
   SIGNAL t2_active : std_logic ;
   SIGNAL data_reg : std_logic_vector(7 DOWNTO 0) ;
   SIGNAL indir_2nd : std_logic ;
   SIGNAL second_result : std_logic ;

   TYPE state_type IS (
      decode_state,
      short,
      strobe_gb,
      read_gb,
      alu_wait,
      read2_gb,
      strobe2_gb,
      put_addr_dst,
      output_data,
      instr_done,
      write_to_gb,
      strobe_gb1,
      read_gb1
   );

   -- State vector declaration
   ATTRIBUTE state_vector : string;
   ATTRIBUTE state_vector OF fsm : architecture IS "current_state" ;


   -- Declare current and next state signals
   SIGNAL current_state, next_state : state_type ;

   -- Declare any pre-registered internal signals
   SIGNAL bit_loc_int : std_logic_vector(2 DOWNTO 0) ;

BEGIN

   ----------------------------------------------------------------------------
   clocked : PROCESS (
      int_clk,
      cpu_rst
   )
   ----------------------------------------------------------------------------
   BEGIN
      IF (cpu_rst = '1') THEN
         current_state <= decode_state;
         -- Reset Values
         bit_loc <= "000";
         data_reg <= "00000000";
         data_tmp <= "000";
         indir_2nd <= '0';
         second_result <= '0';
         t1_active <= '0';
         t2_active <= '1';
         t_cmd <= "0000";
      ELSIF (int_clk'EVENT AND int_clk = '1') THEN
         current_state <= next_state;
         -- Registered output assignments
         bit_loc <= bit_loc_int;

         -- Default Assignment To Internals
         data_reg <= data_reg;
         indir_2nd <= indir_2nd;
         second_result <= second_result;
         t1_active <= t1_active;
         t2_active <= t2_active;

         -- State Actions for internal signals only
         CASE current_state IS
         WHEN short =>
            CASE t_cmd IS
   WHEN use_acc =>
      data_reg <= acc;
   WHEN OTHERS =>
       data_reg <= "00000000";
END CASE;
         WHEN read_gb =>
            data_reg <= data_gb;
         WHEN read2_gb =>
            data_reg <= data_gb;
         WHEN read_gb1 =>
            data_reg <= data_gb;
         WHEN OTHERS =>
            NULL;
         END CASE;

         -- Transition Actions for internal signals only
         CASE current_state IS
         WHEN alu_wait =>
            IF (t2_active = '1') THEN
               t2_active <= '0';
               t1_active <= '1';
            ELSIF (dest_cmd = nothing) THEN
               t1_active <= '0';
            ELSE
               t1_active <= '0';
               second_result <= '0';
            END IF;
         WHEN put_addr_dst =>
            IF (dest_cmd = indirect_T) THEN
               indir_2nd <= '1';
            END IF;
         WHEN output_data =>
            indir_2nd <= '0';
         WHEN instr_done =>
            IF (new_ir = '1') THEN
               t2_active <= '1';
            END IF;
         WHEN write_to_gb =>
            IF (two_dests='1' AND second_result = '0') THEN
               second_result <= '1';
            END IF;
         WHEN OTHERS =>
            NULL;
         END CASE;

      END IF;

   END PROCESS clocked;

   ----------------------------------------------------------------------------
   nextstate : PROCESS (
      current_state,
      data_tmp,
      t_cmd,
      t1_active,
      t2_active,
      data_reg,
      indir_2nd,
      second_result,
      data_gb,
      acc,
      rs,
      acknow,
      alu_result,
      two_dests,
      dest_cmd,
      data_dest,
      t2_cmd,
      data_t2,
      data_t1,
      new_ir,
      t1_cmd
   )
   ----------------------------------------------------------------------------
   BEGIN
      CASE current_state IS
      WHEN decode_state =>
         IF (t_cmd = use_acc OR t_cmd = zeros OR t_cmd = nothing

) THEN
            next_state <= short;
         ELSE
            next_state <= strobe_gb;
         END IF;
      WHEN short =>
            next_state <= alu_wait;
      WHEN strobe_gb =>
         IF (acknow = '1') THEN
            next_state <= read_gb;
         ELSE
            next_state <= strobe_gb;
         END IF;
      WHEN read_gb =>
         IF (t_cmd = bit_addr OR
 (t_cmd(3) = '1' AND t_cmd(2) = '1')) THEN
            next_state <= strobe2_gb;
         ELSE
            next_state <= alu_wait;
         END IF;
      WHEN alu_wait =>
         IF (t2_active = '1') THEN
            next_state <= decode_state;
         ELSIF (dest_cmd = nothing) THEN
            next_state <= instr_done;
         ELSE
            next_state <= output_data;
         END IF;
      WHEN read2_gb =>
            next_state <= alu_wait;
      WHEN strobe2_gb =>
         IF (acknow = '1') THEN
            next_state <= read2_gb;
         ELSE
            next_state <= strobe2_gb;
         END IF;
      WHEN put_addr_dst =>
         IF (dest_cmd = same_as_t1 OR dest_cmd = direct_T OR
dest_cmd = use_reg OR indir_2nd = '1') THEN
            next_state <= write_to_gb;
         ELSIF (dest_cmd = indirect_T) THEN
            next_state <= strobe_gb1;
         ELSE
            next_state <= put_addr_dst;
         END IF;
      WHEN output_data =>
         IF (dest_cmd = use_acc OR dest_cmd = wr_at_sp) THEN
            next_state <= write_to_gb;
         ELSIF (dest_cmd = direct_T) THEN
            next_state <= strobe_gb1;
         ELSE
            next_state <= put_addr_dst;
         END IF;
      WHEN instr_done =>
         IF (new_ir = '1') THEN
            next_state <= decode_state;
         ELSE
            next_state <= instr_done;
         END IF;
      WHEN write_to_gb =>
         IF (two_dests='1' AND second_result = '0') THEN
            next_state <= output_data;
         ELSE
            next_state <= instr_done;
         END IF;
      WHEN strobe_gb1 =>
         IF (acknow = '1') THEN
            next_state <= read_gb1;
         ELSE
            next_state <= strobe_gb1;
         END IF;
      WHEN read_gb1 =>
            next_state <= put_addr_dst;
      END CASE;

   END PROCESS nextstate;

   ----------------------------------------------------------------------------
   output : PROCESS (
      current_state,
      data_tmp,
      t_cmd,
      t1_active,
      t2_active,
      data_reg,
      indir_2nd,
      second_result,
      data_gb,
      acc,
      rs,
      acknow,
      alu_result,
      two_dests,
      dest_cmd,
      data_dest,
      t2_cmd,
      data_t2,
      data_t1,
      new_ir,
      t1_cmd
   )
   ----------------------------------------------------------------------------
   BEGIN
      -- Default Assignment
      addr_gb <= "ZZZZZZZZ";
      cpu_done <= '0';
      dec_rd_sp <= 'Z';
      inc_wr_sp <= 'Z';
      indirect_sel <= 'Z';
      rd_gb <= 'Z';
      rd_pmem1 <= 'Z';
      rd_pmem2 <= 'Z';
      tmp1_done <= '0';
      wr_acc <= 'Z';
      wr_gb <= 'Z';
      wr_out <= '0';

      -- State Actions
      CASE current_state IS
      WHEN strobe_gb =>
         CASE t_cmd IS
   WHEN immed | direct_T | bit_addr =>
      rd_pmem1 <= data_tmp(0);
      rd_pmem2 <= NOT data_tmp(0);
   WHEN rd_at_sp =>
      dec_rd_sp <= '1';
   WHEN OTHERS =>
      addr_gb <= "000" & rs & data_tmp;
      rd_gb <= '1';
END CASE;
      WHEN alu_wait =>
         wr_out <= '1';
      WHEN strobe2_gb =>
         IF t_cmd(3) = '1' AND t_cmd(2) = '1' THEN
    addr_gb <= data_reg;
ELSIF data_reg(7) = '0' THEN
    addr_gb <= "0010" & data_reg(6 DOWNTO 3);
    bit_loc_int <= data_reg(2 DOWNTO 0);
ELSE
    addr_gb <= data_reg(7 DOWNTO 3) & "000";
    bit_loc_int <= data_reg(2 DOWNTO 0);
END IF;
         rd_gb <= '1';
      WHEN put_addr_dst =>
         IF indir_2nd = '1' THEN
   addr_gb <= data_reg;
ELSE 
   CASE dest_cmd IS
   WHEN same_as_t1 | direct_T => 
       addr_gb <= data_reg;
   WHEN OTHERS    => 
       addr_gb <= "000"&rs&data_dest;
   END CASE;
END IF;
      WHEN output_data =>
         data_gb <= alu_result;
      WHEN instr_done =>
         cpu_done <= '1';
      WHEN write_to_gb =>
         CASE dest_cmd IS
   WHEN use_acc => wr_acc <= '1';
   WHEN wr_at_sp => inc_wr_sp <= '1';
   WHEN OTHERS => wr_gb <= '1';
END CASE;
      WHEN strobe_gb1 =>
         IF dest_cmd = indirect_T THEN
  rd_gb <= '1';
ELSE
  rd_pmem1 <= data_tmp(0);
  rd_pmem2 <= NOT data_tmp(0);
END IF;
      WHEN OTHERS =>
         NULL;
      END CASE;

   END PROCESS output;

   -- Concurrent Statements
data_tmp <= data_t2 WHEN t2_active = '1' ELSE
            data_t1 WHEN t1_active = '1' ELSE
            data_dest;
t_cmd    <= t2_cmd WHEN t2_active = '1' ELSE
            t1_cmd WHEN t1_active = '1' ELSE
            dest_cmd;
alu_second_result <= second_result;

END fsm;