?? 89_full_adder_stim.vhd
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--------------------------------------------------------------------------------
--
-- FULL adder Benchmark -- Simulation Vectors
--
--
-- Authors :
-- Beijing Institute of Technology, Beijing
--
-- Written on Sept. , 20th 1998
--
--
-- Modified on
--
--------------------------------------------------------------------------------
entity E is
end;
architecture AAA of E is
Component FULL_Adder
port (
A : in BIT_VECTOR(3 downto 0);
B : in BIT_VECTOR(3 downto 0);
Cin : in BIT;
S : out BIT_VECTOR(3 downto 0);
Cout : out BIT);
end component;
signal sA , sB ,sS : BIT_VECTOR(3 downto 0);
signal sCin , sCout : BIT ;
signal sC : BIT_VECTOR(3 downto 0) ;
signal sT : BIT_VECTOR(3 downto 0) ;
signal sG : BIT_VECTOR(3 downto 0) ;
for all : FULL_ADDER use entity work.FULL_ADDER(FULL_ADDER) ;
begin
FULL_ADDER1 : FULL_ADDER port map (sA,sB,sCin,sS,sCout);
------- The Clock Process --------------
process
begin
-- test vector 0: 0000+0000+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "0000" ;
sCin <= '0' ;
-- test vector 1: 0000+0001+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "0001" ;
sCin <= '0' ;
-- test vector 2: 0000+0010+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "0010" ;
sCin <= '0' ;
-- test vector 3: 0000+0011+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "0011" ;
sCin <= '0' ;
-- test vector 4: 0000+0100+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "0100" ;
sCin <= '0' ;
-- test vector 5: 0000+0101+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "0101" ;
sCin <= '0' ;
-- test vector 6: 0000+0110+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "0110" ;
sCin <= '0' ;
-- test vector 7: 0000+0111+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "0111" ;
sCin <= '0' ;
-- test vector 8: 0000+1000+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "1000" ;
sCin <= '0' ;
-- test vector 9: 0000+1001+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "1001" ;
sCin <= '0' ;
-- test vector a: 0000+1010+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "1010" ;
sCin <= '0' ;
-- test vector b: 0000+1011+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "1011" ;
sCin <= '0' ;
-- test vector c: 0000+1100+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "1100" ;
sCin <= '0' ;
-- test vector d: 0000+1101+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "1101" ;
sCin <= '0' ;
-- test vector e: 0000+1110+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "1110" ;
sCin <= '0' ;
-- test vector f: 0000+1111+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "1111" ;
sCin <= '0' ;
-- test vector 10: 0101+0000+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "0000" ;
sCin <= '0' ;
-- test vector 11: 1010+0001+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "0001" ;
sCin <= '0' ;
-- test vector 12: 1010+0010+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "0010" ;
sCin <= '0' ;
-- test vector 13: 1010+0011+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "0011" ;
sCin <= '0' ;
-- test vector 14: 1010+0100+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "0100" ;
sCin <= '0' ;
-- test vector 15: 1010+0101+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "0101" ;
sCin <= '0' ;
-- test vector 6: 1010+0110+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "0110" ;
sCin <= '0' ;
-- test vector 17: 1010+0111+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "0111" ;
sCin <= '0' ;
-- test vector 18: 1010+1000+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "1000" ;
sCin <= '0' ;
-- test vector 19: 1010+1001+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "1001" ;
sCin <= '0' ;
-- test vector 1a: 1010+1010+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "1010" ;
sCin <= '0' ;
-- test vector 1b: 1010+1011+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "1011" ;
sCin <= '0' ;
-- test vector 1c: 1010+1100+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "1100" ;
sCin <= '0' ;
-- test vector 1d: 1010+1101+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "1101" ;
sCin <= '0' ;
-- test vector 1e: 1010+1110+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "1110" ;
sCin <= '0' ;
-- test vector 1f: 1010+1111+0
wait for 10 ns ;
sA <= "1010" ;
sB <= "1111" ;
sCin <= '0' ;
-- test vector 20: 1111+0000+1
wait for 10 ns ;
sA <= "1111" ;
sB <= "0000" ;
sCin <= '1' ;
-- test vector 21: 1111+0001+1
wait for 10 ns ;
sA <= "1111" ;
sB <= "0001" ;
sCin <= '1' ;
-- test vector 22: 1111+0010+1
wait for 10 ns ;
sA <= "1111" ;
sB <= "0010" ;
sCin <= '1' ;
-- test vector 23: 1111+0011+0
wait for 10 ns ;
sA <= "0000" ;
sB <= "0011" ;
sCin <= '1' ;
-- test vector 24: 1111+0100+0
wait for 10 ns ;
sA <= "1111" ;
sB <= "0100" ;
sCin <= '1' ;
-- test vector 25: 1111+0101+1
wait for 10 ns ;
sA <= "1111" ;
sB <= "0101" ;
sCin <= '1' ;
-- test vector 26: 1111+0110+1
wait for 10 ns ;
sA <= "1111" ;
sB <= "0110" ;
sCin <= '1' ;
-- test vector 27: 1111+0111+1
wait for 10 ns ;
sA <= "1111" ;
sB <= "0111" ;
sCin <= '1' ;
-- test vector 28: 1111+1000+1
wait for 10 ns ;
sA <= "1111" ;
sB <= "1000" ;
sCin <= '1' ;
-- test vector 29: 1111+1001+1
wait for 10 ns ;
sA <= "1111" ;
sB <= "1001" ;
sCin <= '1' ;
-- test vector 2a: 1111+1010+1
wait for 10 ns ;
sA <= "1111" ;
sB <= "1010" ;
sCin <= '1' ;
-- test vector 2b: 1111+1011+1
wait for 10 ns ;
sA <= "1111" ;
sB <= "1011" ;
sCin <= '1' ;
-- test vector 2c: 1111+1100+1
wait for 10 ns ;
sA <= "1111" ;
sB <= "1100" ;
sCin <= '1' ;
-- test vector 2d: 1111+1101+1
wait for 10 ns ;
sA <= "1111" ;
sB <= "1101" ;
sCin <= '1' ;
-- test vector 2e: 1111+1110+1
wait for 10 ns ;
sA <= "1111" ;
sB <= "1110" ;
sCin <= '1' ;
-- test vector 2f: 1111+1111+1
wait for 10 ns ;
sA <= "1111" ;
sB <= "1111" ;
sCin <= '1' ;
--
assert false
report "---End of Simulation---"
severity error;
end process ;
end AAA;
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