use work.bit_rtl_pkg.all;---------------------------------------- MUX2--     2 select 1  multiplexer--------------------------------------entity bit_rtl_mux2 is port (   in1 : in bit_vector;   in2 : in bit_vector;   pout : out bit_vector;   cnt1: in bit );end bit_rtl_mux2;architecture func of bit_rtl_mux2 isbegin   pout <= in1 when cnt1 ='0' else		  in2;end  func;---------------------------------------- MUX2     bit--     2 select 1  multiplexer--------------------------------------entity bit_rtl_mux2_bit is port (   in1 : in bit;   in2 : in bit;   pout : out bit;   cnt1: in bit );end bit_rtl_mux2_bit;architecture func of bit_rtl_mux2_bit isbegin   pout <= in1 when cnt1 ='0' else		  in2;end  func;---------------------------------------- MUX4--     4 select 1  multiplexer--------------------------------------entity bit_rtl_mux4 is port (   in1 : in bit_vector ;   in2 : in bit_vector ;   in3 : in bit_vector ;   in4 : in bit_vector ;   pout : out bit_vector;   cnt2: in bit;   cnt1: in bit );end bit_rtl_mux4;architecture func of bit_rtl_mux4 isbegin   pout <= in1 when cnt2 ='0' and cnt1='0' else		  in2 when cnt2 ='0' and cnt1='1' else		  in3 when cnt2 ='1' and cnt1='0' else		  in4 ;end  func;---------------------------------------- MUX4 bit--     4 select 1  multiplexer--------------------------------------entity bit_rtl_mux4_bit is port (   in1 : in bit ;   in2 : in bit ;   in3 : in bit ;   in4 : in bit := '0';   pout : out bit;   cnt2: in bit;   cnt1: in bit );end bit_rtl_mux4_bit;architecture func of bit_rtl_mux4_bit isbegin   pout <= in1 when cnt2 ='0' and cnt1='0' else		  in2 when cnt2 ='0' and cnt1='1' else		  in3 when cnt2 ='1' and cnt1='0' else		  in4 ;end  func;use work.bit_rtl_pkg.all;---------------------------------------- MUX8--     8 select 1  multiplexer--------------------------------------entity bit_rtl_mux8 is port (   in1 : in bit_vector  ;   in2 : in bit_vector  ;   in3 : in bit_vector  ;   in4 : in bit_vector  ;   in5 : in bit_vector  ;   in6 : in bit_vector  ;   in7 : in bit_vector  ;   in8 : in bit_vector  ;   pout : out bit_vector;   cnt3: in bit;   cnt2: in bit;   cnt1: in bit );end bit_rtl_mux8;architecture func of bit_rtl_mux8 isbegin   pout <= in1 when cnt3 ='0' and cnt2 ='0' and cnt1='0' else           in2 when cnt3 ='0' and cnt2 ='0' and cnt1='1' else           in3 when cnt3 ='0' and cnt2 ='1' and cnt1='0' else           in4 when cnt3 ='0' and cnt2 ='1' and cnt1='1' else           in5 when cnt3 ='1' and cnt2 ='0' and cnt1='0' else           in6 when cnt3 ='1' and cnt2 ='0' and cnt1='1' else           in7 when cnt3 ='1' and cnt2 ='1' and cnt1='0' else           --in8 when cnt3 ='1' and cnt2 ='1' and cnt1='1' else           in8 ;end  func;use work.bit_rtl_pkg.all;---------------------------------------- MUX16--     16 select 1  multiplexer--------------------------------------entity bit_rtl_mux16 is port (   in1 : in bit_vector ;   in2 : in bit_vector ;   in3 : in bit_vector ;   in4 : in bit_vector ;   in5 : in bit_vector ;   in6 : in bit_vector ;   in7 : in bit_vector ;   in8 : in bit_vector ;   in9 : in bit_vector ;   in10: in bit_vector ;   in11: in bit_vector ;   in12: in bit_vector ;   in13: in bit_vector ;   in14: in bit_vector ;   in15: in bit_vector ;   in16: in bit_vector ;   pout : out bit_vector;   cnt4: in bit;   cnt3: in bit;   cnt2: in bit;   cnt1: in bit );end bit_rtl_mux16;architecture func of bit_rtl_mux16 isbegin   pout <= in1  when cnt4='0' and cnt3 ='0' and cnt2 ='0' and cnt1='0' else           in2  when cnt4='0' and cnt3 ='0' and cnt2 ='0' and cnt1='1' else           in3  when cnt4='0' and cnt3 ='0' and cnt2 ='1' and cnt1='0' else           in4  when cnt4='0' and cnt3 ='0' and cnt2 ='1' and cnt1='1' else           in5  when cnt4='0' and cnt3 ='1' and cnt2 ='0' and cnt1='0' else           in6  when cnt4='0' and cnt3 ='1' and cnt2 ='0' and cnt1='1' else           in7  when cnt4='0' and cnt3 ='1' and cnt2 ='1' and cnt1='0' else           in8  when cnt4='0' and cnt3 ='1' and cnt2 ='1' and cnt1='1' else           in9  when cnt4='1' and cnt3 ='0' and cnt2 ='0' and cnt1='0' else           in10 when cnt4='1' and cnt3 ='0' and cnt2 ='0' and cnt1='1' else           in11 when cnt4='1' and cnt3 ='0' and cnt2 ='1' and cnt1='0' else           in12 when cnt4='1' and cnt3 ='0' and cnt2 ='1' and cnt1='1' else           in13 when cnt4='1' and cnt3 ='1' and cnt2 ='0' and cnt1='0' else           in14 when cnt4='1' and cnt3 ='1' and cnt2 ='0' and cnt1='1' else           in15 when cnt4='1' and cnt3 ='1' and cnt2 ='1' and cnt1='0' else           in16;end  func;use work.bit_rtl_pkg.all;----------------------------------------  Adder--     --------------------------------------entity bit_rtl_adder is   port ( 	  in1  : bit_vector;	  in2  : bit_vector;	  cntl : bit;	  pout : out bit_vector   );end bit_rtl_adder;  architecture func of bit_rtl_adder isbegin   process(cntl)   begin	  if (cntl = '1') then		 pout <= in1+in2;      end if;   end process;end  func;use work.bit_rtl_pkg.all;----------------------------------------  Adder--     no control ports   --------------------------------------entity bit_rtl_adder_nc is   port ( 	  in1  : bit_vector;	  in2  : bit_vector;	  pout : out bit_vector   );end bit_rtl_adder_nc;  architecture func of bit_rtl_adder_nc isbegin   process(in1,in2)   begin	  pout <= in1+in2 after 1 ns;   end process;end  func;use work.bit_rtl_pkg.all;----------------------------------------  Subsracter--     --------------------------------------entity bit_rtl_substracter is   port ( 	  in1  : bit_vector;	  in2  : bit_vector;	  cntl : bit;	  pout : out bit_vector   );end bit_rtl_substracter;  architecture func of bit_rtl_substracter isbegin   process(cntl)   begin	  if (cntl = '1') then		 pout <= in1-in2 after 1 ns ;      end if;   end process;end  func;use work.bit_rtl_pkg.all;----------------------------------------  Subsracter--     no control ports   --------------------------------------entity bit_rtl_substracter_nc is   port ( 	  in1  : bit_vector;	  in2  : bit_vector;	  pout : out bit_vector   );end bit_rtl_substracter_nc;  architecture func of bit_rtl_substracter_nc isbegin   process(in1,in2)   begin	  pout <= in1-in2 after 1 ns;   end process;end  func;use work.bit_rtl_pkg.all;----------------------------------------  Multiplier--     --------------------------------------entity bit_rtl_multiplier is   port ( 	  in1  : bit_vector;	  in2  : bit_vector;	  cntl : bit;	  pout : out bit_vector   );end bit_rtl_multiplier;  architecture func of bit_rtl_multiplier isbegin   process(cntl)   begin	  if (cntl = '1') then		 pout <= in1*in2;      end if;   end process;end  func;use work.bit_rtl_pkg.all;----------------------------------------  Multiplier--    no control ports --------------------------------------entity bit_rtl_multiplier_nc is   port ( 	  in1  : bit_vector;	  in2  : bit_vector;	  pout : out bit_vector   );end bit_rtl_multiplier_nc;  architecture func of bit_rtl_multiplier_nc isbegin   process(in1,in2)   begin	  pout <= in1*in2 after 1 ns;   end process;end  func;use work.bit_rtl_pkg.all;----------------------------------------  Divider--     --------------------------------------entity bit_rtl_divider is   port ( 	  in1  : bit_vector;	  in2  : bit_vector;	  cntl : bit;	  pout : out bit_vector   );end bit_rtl_divider;architecture func of bit_rtl_divider isbegin   process(cntl)   begin	  if (cntl = '1') then		 pout <= in1 - in2;      end if;   end process;end  func;use work.bit_rtl_pkg.all;----------------------------------------  Divider--    no control ports --------------------------------------entity bit_rtl_divider_nc is   port ( 	  in1  : bit_vector;	  in2  : bit_vector;	  pout : out bit_vector   );end bit_rtl_divider_nc;architecture func of bit_rtl_divider_nc isbegin   process(in1,in2)   begin	  pout <= in1 / in2 after 1 ns;   end process;end  func;use work.bit_rtl_pkg.all;----------------------------------------  comparator : <--    no control ports --------------------------------------entity bit_rtl_lt_nc is   port ( 	  in1  : bit_vector;	  in2  : bit_vector;	  pout : out bit   );end bit_rtl_lt_nc;architecture func of bit_rtl_lt_nc isbegin   process(in1,in2)	  variable left : integer;	  variable right: integer;   begin	  left  := bit_to_int(in1);	  right := bit_to_int(in2);	  if ( left < right ) then		 pout <= '1' after 1 ns;      else		 pout <= '0' after 1 ns;      end if;   end process;end  func;use work.bit_rtl_pkg.all;----------------------------------------  comparator : >--    no control ports --------------------------------------entity bit_rtl_gt_nc is   port ( 	  in1  : bit_vector;	  in2  : bit_vector;	  pout : out bit   );end bit_rtl_gt_nc;architecture func of bit_rtl_gt_nc isbegin   process(in1,in2)	  variable left : integer;	  variable right: integer;   begin	  left  := bit_to_int(in1);	  right := bit_to_int(in2);	  if ( left > right ) then		 pout <= '1' after 1 ns;      else		 pout <= '0' after 1 ns;      end if;   end process;end  func;use work.bit_rtl_pkg.all;----------------------------------------  comparator : =--    no control ports --------------------------------------entity bit_rtl_eq_nc is   port ( 	  in1  : bit_vector;	  in2  : bit_vector;	  pout : out bit   );end bit_rtl_eq_nc;architecture func of bit_rtl_eq_nc isbegin   process(in1,in2)	  variable left : integer;	  variable right: integer;   begin	  left  := bit_to_int(in1);	  right := bit_to_int(in2);	  if ( left = right ) then		 pout <= '1' after 1 ns;      else		 pout <= '0' after 1 ns;      end if;   end process;end  func;use work.bit_rtl_pkg.all;----------------------------------------  comparator : =--    no control ports --------------------------------------entity bit_rtl_neq_nc is   port ( 	  in1  : bit_vector;	  in2  : bit_vector;	  pout : out bit   );end bit_rtl_neq_nc;architecture func of bit_rtl_neq_nc isbegin   process(in1,in2)	  variable left : integer;	  variable right: integer;   begin	  left  := bit_to_int(in1);	  right := bit_to_int(in2);	  if ( left = right ) then		 pout <= '0' after 1 ns;      else		 pout <= '1' after 1 ns;      end if;   end process;end  func;use work.bit_rtl_pkg.all;----------------------------------------  comparator : <=--    no control ports --------------------------------------entity bit_rtl_le_nc is   port ( 	  in1  : bit_vector;	  in2  : bit_vector;	  pout : out bit   );end bit_rtl_le_nc;architecture func of bit_rtl_le_nc isbegin   process(in1,in2)	  variable left : integer;	  variable right: integer;   begin	  left  := bit_to_int(in1);	  right := bit_to_int(in2);	  if ( left > right ) then		 pout <= '0' after 1 ns;      else		 pout <= '1' after 1 ns;      end if;   end process;end  func;use work.bit_rtl_pkg.all;----------------------------------------  comparator : >=--    no control ports --------------------------------------entity bit_rtl_ge_nc is   port ( 	  in1  : bit_vector;	  in2  : bit_vector;	  pout : out bit   );end bit_rtl_ge_nc;architecture func of bit_rtl_ge_nc isbegin   process(in1,in2)	  variable left : integer;	  variable right: integer;   begin	  left  := bit_to_int(in1);	  right := bit_to_int(in2);	  if ( left < right ) then		 pout <= '0' after 1 ns;      else		 pout <= '1' after 1 ns;      end if;   end process;end  func;----------------------------------------  Register--     --------------------------------------entity bit_rtl_reg is   port ( 	  pin  : bit_vector;	  cntl : bit;	  pout : out bit_vector   );end bit_rtl_reg;architecture func of bit_rtl_reg isbegin   process(pin,cntl)   begin	  if (cntl = '1') then		 pout <= pin;      end if;   end process;end func;----------------------------------------  Register--    with clock port --------------------------------------entity bit_rtl_reg_clk is   port ( 	  pin  : bit_vector;	  cntl : bit;	  clk  : bit;	  pout : out bit_vector   );end bit_rtl_reg_clk;architecture func of bit_rtl_reg_clk isbegin   process   begin	  wait until clk'event and clk ='1';	  if (cntl = '1') then		 pout <= pin ;      end if;   end process;end func;----------------------------------------  Register bit--    with clock port --------------------------------------entity bit_rtl_reg_clk_bit is   port ( 	  pin  : bit;	  cntl : bit;	  clk  : bit;	  pout : out bit   );end bit_rtl_reg_clk_bit;architecture func of bit_rtl_reg_clk_bit isbegin   process   begin	  wait until clk'event and clk ='1';	  if (cntl = '1') then		 pout <= pin ;      end if;   end process;end func;