module encode(key_reg, op_reg, hold, a0, a1, a2, a3, b0, b1, b2 ,b3);	input a0, a1, a2, a3;	input b0, b1, b2, b3;       										//4*4 input 	output[31:0] key_reg ;	output[5:0] op_reg ;	output hold ; 												//32bit float register output & 																									//6 bit operator register output	reg [5:0]op_reg;	reg [31:0] key_reg ;	reg [39:0] binary_reg ;                         //32bit non-float register, saving mantissa of 																									//key_reg is 32bit float register. 	reg [4:0]	dec_reg [0:9] ;	wire[3:0] AX ;																	//a0~a4 encode ax 	wire[1:0] BX ;																	//b0~b3 encode bx		integer x=0 ; 																	//	reg [4:0] point=0 ;															//this is a register that is bit of a numeral 																									//will be point  	reg hold =0;																			//this resgister enable a end of scaning of numeral		//encoding logic of what is "a[0~4]&b[0~3] -> ax[0~3]&bx[0~1]"	FRISTCODE F_CODE(.a0(a0), .a1(a1), .a2(a2), . a3(a3), .a4(a4), 						.b0(b0), .b1(b1), .b2(b2), .b3(b3), 						.reg_ax(AX), .reg_bx(BX),);	//encoding logic of what is scaned operator of 6bit	always @((ax=0&bx=11)or                         // +				   (ax=1&bx=11)or													// -				   (ax=10&bx=11)or												// *				   (ax=11&bx=11)or 												// /				   (ax=11&bx=10))                         // =   	begin   		OP_REG scan_op (.op_reg(op_reg), ax(AX), bx(BX),);   //obtain a op 			hold = ~hold;																		entd						//translation logic  of what is 'ax[0~3]&bx[0~1] -> 32bit float numeral(1-4-27)' 	//and record bit of point of that numral and its sign. 	always  		begin			if (hold)				beign                                   //while hold is low,'encode' cell seriatim scan numeral 					while( x<10 )                             //max bit is displaied is 10 numbers							begin: scan_logic			 					 		  		//scan_data logic is used for seriatim scaning ax&bx in order to 			 		  		//seriatim translate their to dec_reg[x].			 					KEY_REG scan_date (.dec_reg(dec_reg[x]), ax(AX), bx(BX),); 			 					 					//OP_REG scan_op (.op_reg(op_reg), ax(AX), bx(BX),);	       	        	  	if(op_reg=110 & !counter)             //this logic is used for counting point of numeral 	          			begin             				point=x;             				x=x+1;	          			end	         		  else	          			x=x+1;				 					    				    			if(op_reg=111)											 	//this logic is used for scaning sign of numeral              		key_reg[31]= ~key_reg[31];                        		if((ax=0&bx=11)or                         // +				   				 (ax=1&bx=11)or													// -				   				 (ax=10&bx=11)or												// *				      	   (ax=11&bx=11)or 												// /				   				 (ax=11&bx=10))				   				 disable scan_logic ;                           	 end                    hold= ~hold;                  end 			    		  	else																				//while hold is high , all of decimal numerals is translated binary 				begin									//x=0				    				    //	  				binary_reg={dec_reg[9],dec_reg[8],dec_reg[7],dec_reg[6],dec_reg[5],	  										dec_reg[4],dec_reg[3],dec_reg[2],dec_reg[1],dec_reg[0]};	  					//while(x<10)						//begin						//DEC_BINARY DEC_BIN(.sum(dec_reg[x]), .carry(dec_reg[x+1]),																.a(dec_reg[x]), .b(dec-reg[x+1]),) ;    //input data*10 => 1.4.27						//end										//x=0									hold= ~hold;				end	  		  		  		  	key_reg[26:0] = binary_reg ; 								//because binary max is 1024*1024*128 is less than 2e27 					key_reg[30:27] = point ;  	 	  end	  	  	endmodule	;primitive KEY_REG (dec_reg, ax, bx);	input ax, bx;	output dec_reg；	reg[9:0] dec_reg;  	table		0  0  : 4'b111 ;  														//0 0 -> 7		0  1  : 4'b1000;															//0 1 -> 8		0  11 : 4'b1001;															//0 2 -> 9		1  0  : 4'b100 ;															//1 0 -> 4		1  1  : 4'b101 ;															//1 1 -> 5		1  11 : 4'b110 ;															//1 2 -> 6		11 0  : 4'b1 ;																//2 0 -> 1		11 1  : 4'b10 ;																//2 1 -> 2		11 11 : 4'b11 ;																//2 2 -> 3		100 0 : 4'b0 ; 																//3 0 -> 0	endtableendprimitive	primitive OP_REG(op_reg, ax, bx);	input ax, bx ;	output op_reg ;	reg[5:0] op_reg ;		table			0   11 : 6'b10 ;															//0 3 -> +				1   11 : 6'b11 ;															//1 3 -> -				10  11 : 6'b100 ;															//2 3 -> *				11  1  : 6'b110 ;															//3 1 -> .		11  10 : 6'b1 ;																//3 2 -> =		11  11 : 6'b101 ;															//3 3 -> /		100 11 : 6'b111 ;															//4 3 -> sign -	endtableendprimitivemodule FRISTCODE(reg_ax, reg_bx, a0, a1, a2, a3, a4, b0, b1, b2, b3 );	input a0. a1, a2, a3, a4, b0, b1, b2, b3;	output reg_ax, reg_bx ;	reg [3:0] reg_ax ;	reg [1:0] ref_bx ;	reg unconv;                  //		always			if(a0&b0) begin reg_ax=0  ; reg_bx=2'b0 end   			elseif(a0&b1) begin reg_ax=4'b0  ; reg_bx=2'b1 end		elseif(a0&b2) begin reg_ax=4'b0  ; reg_bx=2'b11 end		elaeif(a0&b3) begin reg_ax=4'b0  ; reg_bx=2'b100 end				elseif(a1&b0) begin reg_ax=4'b1  ; reg_bx=2'b0 end		elseif(a1&b1) begin reg_ax=4'b1  ; reg_bx=2'b1 end		elaeif(a1&b2) begin reg_ax=4'b1  ; reg_bx=2'b11 end		elseif(a1&b3) begin reg_ax=4'b1  ; reg_bx=2'b100 end				elseif(a2&b0) begin reg_ax=4'b10  ; reg_bx=2'b0 end		elseif(a2&b1) begin reg_ax=4'b10  ; reg_bx=2'b1 end		elseif(a2&b2) begin reg_ax=4'b10  ; reg_bx=2'b11 end		elseif(a2&b3) begin reg_ax=4'b10  ; reg_bx=2'b100 end				elseif(a3&b0) begin reg_ax=4'b11  ; reg_bx=2'b0 end		elseif(a3&b1) begin reg_ax=4'b11  ; reg_bx=2'b1 end		elseif(a3&b2) begin reg_ax=4'b11  ; reg_bx=2'b11 end		elseif(a3&b3) begin reg_ax=4'b11  ; reg_bx=2'b100 end				elseif(a4&b0) begin reg_ax=4'b100  ; reg_bx=2'b0 end    elseif(a4&b1) begin reg_ax=4'b100  ; reg_bx=2'b1 end    elseif(a4&b2) begin reg_ax=4'b100  ; reg_bx=2'b11 end    elseif(a4&b3) begin reg_ax=4'b100  ; reg_bx=2'b100 end        else 	unconv=1;endmodule//this logic is used for translating all of decimal numerals to binary numerals.//module DEC_BINARY(carry, sum, a, b,);	//input[3:0] a,b;	//output[7:0] sum;	//output[3:0] carry;		//begin		//sum=a+b ;		//carry=sum[7:4] ;	//end	//endmodule