?? tiaoping.rpt
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Project Information d:\vhdl\tiaoping\tiaoping.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 02/20/2006 12:17:25
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
TIAOPING
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
tiaoping EPM7064TC44-7 23 13 0 34 0 53 %
User Pins: 23 13 0
Project Information d:\vhdl\tiaoping\tiaoping.rpt
** PROJECT COMPILATION MESSAGES **
Info: Design Doctor has given the project a clean bill of health based on the EPLD Rules set
Info: Reserved unused input pin 'tdi' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'tms' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'tdo' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'tck' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'p1_5' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Project Information d:\vhdl\tiaoping\tiaoping.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information d:\vhdl\tiaoping\tiaoping.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
tiaoping@22 addr_out0
tiaoping@21 addr_out1
tiaoping@20 addr_out2
tiaoping@19 addr_out3
tiaoping@37 clk
tiaoping@15 clk_out
tiaoping@42 cpld_sel
tiaoping@34 din0
tiaoping@33 din1
tiaoping@31 din2
tiaoping@30 din3
tiaoping@28 din4
tiaoping@27 din5
tiaoping@25 din6
tiaoping@23 din7
tiaoping@40 d_sel
tiaoping@14 oe_out
tiaoping@8 p1_3
tiaoping@2 p1_4
tiaoping@38 p1_5
tiaoping@39 p1_6
tiaoping@11 rd
tiaoping@44 sel_addr0
tiaoping@43 sel_addr1
tiaoping@3 sel_out0
tiaoping@5 sel_out1
tiaoping@35 sel_out2
tiaoping@6 sel_out3
tiaoping@12 serial_og
tiaoping@13 serial_or
tiaoping@26 tck
tiaoping@1 tdi
tiaoping@32 tdo
tiaoping@7 tms
tiaoping@10 wr
tiaoping@18 xlat
Project Information d:\vhdl\tiaoping\tiaoping.rpt
** FILE HIERARCHY **
|lpm_add_sub:627|
|lpm_add_sub:627|addcore:adder|
|lpm_add_sub:627|addcore:adder|addcore:adder0|
|lpm_add_sub:627|altshift:result_ext_latency_ffs|
|lpm_add_sub:627|altshift:carry_ext_latency_ffs|
|lpm_add_sub:627|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:669|
|lpm_add_sub:669|addcore:adder|
|lpm_add_sub:669|addcore:adder|addcore:adder0|
|lpm_add_sub:669|altshift:result_ext_latency_ffs|
|lpm_add_sub:669|altshift:carry_ext_latency_ffs|
|lpm_add_sub:669|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:711|
|lpm_add_sub:711|addcore:adder|
|lpm_add_sub:711|addcore:adder|addcore:adder0|
|lpm_add_sub:711|altshift:result_ext_latency_ffs|
|lpm_add_sub:711|altshift:carry_ext_latency_ffs|
|lpm_add_sub:711|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:753|
|lpm_add_sub:753|addcore:adder|
|lpm_add_sub:753|addcore:adder|addcore:adder0|
|lpm_add_sub:753|altshift:result_ext_latency_ffs|
|lpm_add_sub:753|altshift:carry_ext_latency_ffs|
|lpm_add_sub:753|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:795|
|lpm_add_sub:795|addcore:adder|
|lpm_add_sub:795|addcore:adder|addcore:adder0|
|lpm_add_sub:795|altshift:result_ext_latency_ffs|
|lpm_add_sub:795|altshift:carry_ext_latency_ffs|
|lpm_add_sub:795|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:837|
|lpm_add_sub:837|addcore:adder|
|lpm_add_sub:837|addcore:adder|addcore:adder0|
|lpm_add_sub:837|altshift:result_ext_latency_ffs|
|lpm_add_sub:837|altshift:carry_ext_latency_ffs|
|lpm_add_sub:837|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:879|
|lpm_add_sub:879|addcore:adder|
|lpm_add_sub:879|addcore:adder|addcore:adder0|
|lpm_add_sub:879|altshift:result_ext_latency_ffs|
|lpm_add_sub:879|altshift:carry_ext_latency_ffs|
|lpm_add_sub:879|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1187|
|lpm_add_sub:1187|addcore:adder|
|lpm_add_sub:1187|addcore:adder|addcore:adder0|
|lpm_add_sub:1187|altshift:result_ext_latency_ffs|
|lpm_add_sub:1187|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1187|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1229|
|lpm_add_sub:1229|addcore:adder|
|lpm_add_sub:1229|addcore:adder|addcore:adder0|
|lpm_add_sub:1229|altshift:result_ext_latency_ffs|
|lpm_add_sub:1229|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1229|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1271|
|lpm_add_sub:1271|addcore:adder|
|lpm_add_sub:1271|addcore:adder|addcore:adder0|
|lpm_add_sub:1271|altshift:result_ext_latency_ffs|
|lpm_add_sub:1271|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1271|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1313|
|lpm_add_sub:1313|addcore:adder|
|lpm_add_sub:1313|addcore:adder|addcore:adder0|
|lpm_add_sub:1313|altshift:result_ext_latency_ffs|
|lpm_add_sub:1313|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1313|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1355|
|lpm_add_sub:1355|addcore:adder|
|lpm_add_sub:1355|addcore:adder|addcore:adder0|
|lpm_add_sub:1355|altshift:result_ext_latency_ffs|
|lpm_add_sub:1355|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1355|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1397|
|lpm_add_sub:1397|addcore:adder|
|lpm_add_sub:1397|addcore:adder|addcore:adder0|
|lpm_add_sub:1397|altshift:result_ext_latency_ffs|
|lpm_add_sub:1397|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1397|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1439|
|lpm_add_sub:1439|addcore:adder|
|lpm_add_sub:1439|addcore:adder|addcore:adder0|
|lpm_add_sub:1439|altshift:result_ext_latency_ffs|
|lpm_add_sub:1439|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1439|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2121|
|lpm_add_sub:2121|addcore:adder|
|lpm_add_sub:2121|addcore:adder|addcore:adder0|
|lpm_add_sub:2121|altshift:result_ext_latency_ffs|
|lpm_add_sub:2121|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2121|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\vhdl\tiaoping\tiaoping.rpt
tiaoping
***** Logic for device 'tiaoping' compiled without errors.
Device: EPM7064TC44-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
Device-Specific Information: d:\vhdl\tiaoping\tiaoping.rpt
tiaoping
** ERROR SUMMARY **
Info: Chip 'tiaoping' in device 'EPM7064TC44-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
s s
e e c s
l l p e
_ _ l l
a a d d _
d d _ _ p p o d
d d s V s 1 1 c G u i
r r e C e _ _ l N t n
0 1 l C l 6 5 k D 2 0
-----------------------------------_
/ 44 43 42 41 40 39 38 37 36 35 34 |
tdi | 1 33 | din1
p1_4 | 2 32 | tdo
sel_out0 | 3 31 | din2
GND | 4 30 | din3
sel_out1 | 5 29 | VCC
sel_out3 | 6 EPM7064TC44-7 28 | din4
tms | 7 27 | din5
p1_3 | 8 26 | tck
VCC | 9 25 | din6
wr | 10 24 | GND
rd | 11 23 | din7
|_ 12 13 14 15 16 17 18 19 20 21 22 _|
------------------------------------
s s o c G V x a a a a
e e e l N C l d d d d
r r _ k D C a d d d d
i i o _ t r r r r
a a u o _ _ _ _
l l t u o o o o
_ _ t u u u u
o o t t t t
g r 3 2 1 0
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\vhdl\tiaoping\tiaoping.rpt
tiaoping
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 3/16( 18%) 8/ 8(100%) 0/16( 0%) 5/36( 13%)
B: LC17 - LC32 16/16(100%) 8/ 8(100%) 0/16( 0%) 29/36( 80%)
C: LC33 - LC48 14/16( 87%) 8/ 8(100%) 0/16( 0%) 13/36( 36%)
D: LC49 - LC64 1/16( 6%) 8/ 8(100%) 0/16( 0%) 4/36( 11%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 32/32 (100%)
Total logic cells used: 34/64 ( 53%)
Total shareable expanders used: 0/64 ( 0%)
Total Turbo logic cells used: 34/64 ( 53%)
Total shareable expanders not available (n/a): 0/64 ( 0%)
Average fan-in: 4.61
Total fan-in: 157
Total input pins required: 23
Total output pins required: 13
Total bidirectional pins required: 0
Total logic cells required: 34
Total flipflops required: 23
Total product terms required: 76
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 64 ( 0%)
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