?? tiaoping.rpt
字號:
Device-Specific Information: d:\vhdl\tiaoping\tiaoping.rpt
tiaoping
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
37 - - INPUT G 0 0 0 0 0 0 0 clk
42 (16) (A) INPUT 0 0 0 0 0 7 16 cpld_sel
34 (62) (D) INPUT 0 0 0 0 0 0 1 din0
33 (57) (D) INPUT 0 0 0 0 0 0 1 din1
31 (53) (D) INPUT 0 0 0 0 0 0 1 din2
30 (52) (D) INPUT 0 0 0 0 0 0 1 din3
28 (51) (D) INPUT 0 0 0 0 0 0 1 din4
27 (49) (D) INPUT 0 0 0 0 0 0 1 din5
25 (46) (C) INPUT 0 0 0 0 0 0 1 din6
23 (41) (C) INPUT 0 0 0 0 0 0 1 din7
40 - - INPUT 0 0 0 0 0 2 1 d_sel
8 (30) (B) INPUT 0 0 0 0 0 5 4 p1_3
2 (5) (A) INPUT 0 0 0 0 0 1 0 p1_4
38 - - INPUT 0 0 0 0 0 0 0 p1_5
39 - - INPUT 0 0 0 0 0 0 4 p1_6
11 (24) (B) INPUT 0 0 0 0 0 3 0 rd
44 (11) (A) INPUT 0 0 0 0 0 4 0 sel_addr0
43 (14) (A) INPUT 0 0 0 0 0 4 0 sel_addr1
26 (48) (C) INPUT 0 0 0 0 0 0 0 tck
1 (8) (A) INPUT 0 0 0 0 0 0 0 tdi
32 (56) (D) INPUT 0 0 0 0 0 0 0 tdo
7 (32) (B) INPUT 0 0 0 0 0 0 0 tms
10 (25) (B) INPUT 0 0 0 0 0 5 12 wr
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\vhdl\tiaoping\tiaoping.rpt
tiaoping
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
22 40 C FF t 0 0 0 1 1 0 0 addr_out0
21 37 C FF t 0 0 0 1 1 0 0 addr_out1
20 36 C FF t 0 0 0 1 1 0 0 addr_out2
19 35 C FF t 0 0 0 1 1 0 0 addr_out3
15 17 B FF + t 0 0 0 2 2 1 0 clk_out
14 19 B OUTPUT t 0 0 0 1 0 0 0 oe_out
3 4 A OUTPUT t 0 0 0 3 0 0 0 sel_out0
5 3 A OUTPUT t 0 0 0 5 0 0 0 sel_out1
35 64 D OUTPUT t 0 0 0 4 0 0 0 sel_out2
6 1 A OUTPUT t 0 0 0 5 0 0 0 sel_out3
12 21 B FF + t 0 0 0 3 3 1 0 serial_og
13 20 B FF + t 0 0 0 3 3 1 0 serial_or
18 33 C OUTPUT t 0 0 0 1 0 0 0 xlat
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\tiaoping\tiaoping.rpt
tiaoping
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(25) 46 C SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:879|addcore:adder|addcore:adder0|result_node2
- 44 C SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:1439|addcore:adder|addcore:adder0|result_node2
- 43 C SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:2121|addcore:adder|addcore:adder0|result_node1
- 42 C SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:2121|addcore:adder|addcore:adder0|result_node2
(23) 41 C SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:2121|addcore:adder|addcore:adder0|result_node3
- 23 B DFFE + t 0 0 0 3 3 2 1 tmp87 (:44)
(11) 24 B DFFE + t 0 0 0 3 3 0 2 tmp86 (:45)
- 22 B DFFE + t 0 0 0 3 3 0 2 tmp85 (:46)
- 18 B DFFE + t 0 0 0 3 3 0 2 tmp84 (:47)
(7) 32 B DFFE + t 0 0 0 3 3 0 2 tmp83 (:48)
- 29 B DFFE + t 0 0 0 3 3 0 2 tmp82 (:49)
(10) 25 B DFFE + t 0 0 0 3 3 0 2 tmp81 (:50)
(8) 30 B DFFE + t 0 0 0 3 1 0 2 tmp80 (:51)
- 31 B DFFE + t 0 0 0 2 4 3 11 count_temp3 (:52)
- 26 B DFFE + t 0 0 0 3 4 0 4 count_temp2 (:53)
- 28 B DFFE + t 0 0 0 2 3 0 4 count_temp1 (:54)
- 27 B DFFE + t 0 0 0 2 2 0 5 count_temp0 (:55)
- 34 C DFFE t 0 0 0 3 1 1 1 count_x3 (:56)
- 38 C DFFE t 0 0 0 3 1 1 2 count_x2 (:57)
- 39 C DFFE t 0 0 0 3 1 1 3 count_x1 (:58)
- 45 C TFFE t 0 0 0 3 1 1 4 count_x0 (:59)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\tiaoping\tiaoping.rpt
tiaoping
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----- LC4 sel_out0
| +--- LC3 sel_out1
| | +- LC1 sel_out3
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'A'
LC | | | | A B C D | Logic cells that feed LAB 'A':
Pin
37 -> - - - | - - - - | <-- clk
42 -> * * * | * * * * | <-- cpld_sel
40 -> - - - | - * - - | <-- d_sel
38 -> - - - | - - - - | <-- p1_5
39 -> - - - | - - * - | <-- p1_6
11 -> - * * | * - - * | <-- rd
44 -> * * * | * - - * | <-- sel_addr0
43 -> * * * | * - - * | <-- sel_addr1
10 -> - * * | * * - - | <-- wr
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\tiaoping\tiaoping.rpt
tiaoping
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC17 clk_out
| +----------------------------- LC19 oe_out
| | +--------------------------- LC21 serial_og
| | | +------------------------- LC20 serial_or
| | | | +----------------------- LC23 tmp87
| | | | | +--------------------- LC24 tmp86
| | | | | | +------------------- LC22 tmp85
| | | | | | | +----------------- LC18 tmp84
| | | | | | | | +--------------- LC32 tmp83
| | | | | | | | | +------------- LC29 tmp82
| | | | | | | | | | +----------- LC25 tmp81
| | | | | | | | | | | +--------- LC30 tmp80
| | | | | | | | | | | | +------- LC31 count_temp3
| | | | | | | | | | | | | +----- LC26 count_temp2
| | | | | | | | | | | | | | +--- LC28 count_temp1
| | | | | | | | | | | | | | | +- LC27 count_temp0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC17 -> * - - - - - - - - - - - - - - - | - * - - | <-- clk_out
LC21 -> - - * - - - - - - - - - - - - - | - * - - | <-- serial_og
LC20 -> - - - * - - - - - - - - - - - - | - * - - | <-- serial_or
LC23 -> - - * * * - - - - - - - - - - - | - * - - | <-- tmp87
LC24 -> - - - - * * - - - - - - - - - - | - * - - | <-- tmp86
LC22 -> - - - - - * * - - - - - - - - - | - * - - | <-- tmp85
LC18 -> - - - - - - * * - - - - - - - - | - * - - | <-- tmp84
LC32 -> - - - - - - - * * - - - - - - - | - * - - | <-- tmp83
LC29 -> - - - - - - - - * * - - - - - - | - * - - | <-- tmp82
LC25 -> - - - - - - - - - * * - - - - - | - * - - | <-- tmp81
LC30 -> - - - - - - - - - - * * - - - - | - * - - | <-- tmp80
LC31 -> * - * * * * * * * * * - * * * * | - * - - | <-- count_temp3
LC26 -> - - - - - - - - - - - - * * - - | - * * - | <-- count_temp2
LC28 -> - - - - - - - - - - - - * - * - | - * * - | <-- count_temp1
LC27 -> - - - - - - - - - - - - * - * * | - * * - | <-- count_temp0
Pin
37 -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
42 -> * - * * * * * * * * * * * * * * | * * * * | <-- cpld_sel
34 -> - - - - - - - - - - - * - - - - | - * - - | <-- din0
33 -> - - - - - - - - - - * - - - - - | - * - - | <-- din1
31 -> - - - - - - - - - * - - - - - - | - * - - | <-- din2
30 -> - - - - - - - - * - - - - - - - | - * - - | <-- din3
28 -> - - - - - - - * - - - - - - - - | - * - - | <-- din4
27 -> - - - - - - * - - - - - - - - - | - * - - | <-- din5
25 -> - - - - - * - - - - - - - - - - | - * - - | <-- din6
23 -> - - - - * - - - - - - - - - - - | - * - - | <-- din7
40 -> - - * * - - - - - - - - - * - - | - * - - | <-- d_sel
2 -> - * - - - - - - - - - - - - - - | - * - - | <-- p1_4
38 -> - - - - - - - - - - - - - - - - | - - - - | <-- p1_5
39 -> - - - - - - - - - - - - - - - - | - - * - | <-- p1_6
10 -> * - * * * * * * * * * * * * * * | * * - - | <-- wr
LC46 -> - - - - - - - - - - - - - * - - | - * - - | <-- |LPM_ADD_SUB:879|addcore:adder|addcore:adder0|result_node2
LC44 -> - - - - - - - - - - - - - * - - | - * - - | <-- |LPM_ADD_SUB:1439|addcore:adder|addcore:adder0|result_node2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\tiaoping\tiaoping.rpt
tiaoping
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------------------------- LC40 addr_out0
| +------------------------- LC37 addr_out1
| | +----------------------- LC36 addr_out2
| | | +--------------------- LC35 addr_out3
| | | | +------------------- LC46 |LPM_ADD_SUB:879|addcore:adder|addcore:adder0|result_node2
| | | | | +----------------- LC44 |LPM_ADD_SUB:1439|addcore:adder|addcore:adder0|result_node2
| | | | | | +--------------- LC43 |LPM_ADD_SUB:2121|addcore:adder|addcore:adder0|result_node1
| | | | | | | +------------- LC42 |LPM_ADD_SUB:2121|addcore:adder|addcore:adder0|result_node2
| | | | | | | | +----------- LC41 |LPM_ADD_SUB:2121|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | +--------- LC33 xlat
| | | | | | | | | | | +----- LC38 count_x2
| | | | | | | | | | | | +--- LC39 count_x1
| | | | | | | | | | | | | +- LC45 count_x0
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC43 -> - - - - - - - - - - - - * - | - - * - | <-- |LPM_ADD_SUB:2121|addcore:adder|addcore:adder0|result_node1
LC42 -> - - - - - - - - - - - * - - | - - * - | <-- |LPM_ADD_SUB:2121|addcore:adder|addcore:adder0|result_node2
LC41 -> - - - - - - - - - - * - - - | - - * - | <-- |LPM_ADD_SUB:2121|addcore:adder|addcore:adder0|result_node3
LC34 -> - - - * - - - - * - - - - - | - - * - | <-- count_x3
LC38 -> - - * - - - - * * - - - - - | - - * - | <-- count_x2
LC39 -> - * - - - - * * * - - - - - | - - * - | <-- count_x1
LC45 -> * - - - - - * * * - - - - * | - - * - | <-- count_x0
Pin
37 -> - - - - - - - - - - - - - - | - - - - | <-- clk
42 -> - - - - - - - - - - * * * * | * * * * | <-- cpld_sel
40 -> - - - - - - - - - - - - - - | - * - - | <-- d_sel
8 -> * * * * - - - - - * * * * * | - - * - | <-- p1_3
38 -> - - - - - - - - - - - - - - | - - - - | <-- p1_5
39 -> - - - - - - - - - - * * * * | - - * - | <-- p1_6
LC26 -> - - - - * * - - - - - - - - | - * * - | <-- count_temp2
LC28 -> - - - - * * - - - - - - - - | - * * - | <-- count_temp1
LC27 -> - - - - * * - - - - - - - - | - * * - | <-- count_temp0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\tiaoping\tiaoping.rpt
tiaoping
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+- LC64 sel_out2
|
| Other LABs fed by signals
| that feed LAB 'D'
LC | | A B C D | Logic cells that feed LAB 'D':
Pin
37 -> - | - - - - | <-- clk
42 -> * | * * * * | <-- cpld_sel
40 -> - | - * - - | <-- d_sel
38 -> - | - - - - | <-- p1_5
39 -> - | - - * - | <-- p1_6
11 -> * | * - - * | <-- rd
44 -> * | * - - * | <-- sel_addr0
43 -> * | * - - * | <-- sel_addr1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\tiaoping\tiaoping.rpt
tiaoping
** EQUATIONS **
clk : INPUT;
cpld_sel : INPUT;
din0 : INPUT;
din1 : INPUT;
din2 : INPUT;
din3 : INPUT;
din4 : INPUT;
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